K6R1016C1C-C/C-L, K6R1016C1C-I/C-P

CMOS SRAM

Revision 4.0

- 2 -

September 2001

64K x 16 Bit High-Speed CMOS Static RAM

The K6R1016C1C is a 1,048,576-bit high-speed Static Random

Access Memory organized as 65,536 words by 16 bits. The

K6R1016C1C uses 16 common input and output lines and has

at output enable pin which operates faster than address access

time at read cycle. Also it allows that lower and upper byte

access by data byte control (UB, LB). The device is fabricated

using SAMSUNG

′s advanced CMOS process and designed for

high-speed circuit technology. It is particularly well suited for

use in high-density high-speed system applications. The

K6R1016C1C is packaged in a 400mil 44-pin plastic SOJ or

TSOP2 forward or 48-Fine pitch BGA.

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 10,12,15ns(Max.)

• Low Power Dissipation

Standby (TTL)

: 30mA(Max.)

(CMOS) :

5mA(Max.)

0.5mA(Max.) L-ver. only

Operating K6R1016C1C-10 : 105mA(Max.)

K6R1016C1C-12 : 95mA(Max.)

K6R1016C1C-15 : 93mA(Max.)

• Single 5.0V

±10% Power Supply

• TTL Compatible Inputs and Outputs

• I/O Compatible with 3.3V Device

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• 2V Minimum Data Retention: L-ver. only

• Center Power/Ground Pin Configuration

• Standard Pin Configuration:

K6R1016C1C-J : 44-SOJ-400

K6R1016C1C-T: 44-TSOP2-400BF

K6R1016C1C-F: 48-Fine pitch BGA with 0.75 Ball pitch

Clk Gen.

OE

UB

CS

FUNCTIONAL BLOCK DIAGRAM

Data

Cont.

Column Select

CLK

Gen.

Pre-Charge Circuit

Memory Array

512 Rows

128x16 Columns

I/O Circuit &

Data

Cont.

WE

LB

K6R1016C1C-C10/C12/C15

Commercial Temp.

K6R1016C1C-I10/I12/I15

Industrial Temp.

ORDERING INFORMATION

PIN FUNCTION

Pin Name

Pin Function

Address Inputs

WE

Write Enable

CS

Chip Select

OE

Output Enable

LB

UB

Data Inputs/Outputs

Power(+5.0V)

Ground

N.C

No Connection