TSS901EASLASH883 datasheet(2/31 Pages) ATMEL

2 / 31 page

TSS901E

Rev. C – 24-Aug-01

Introduction

The TSS901E provides an interface between a Data-Strobe link according to the IEEE

Std 1355-1995 specification carrying the simple interprocessor communication proto-

col (1) and a data processing node consisting of a CPU and communication and data

memory. The TSS901E provides HW supported execution of the major parts of the sim-

ple interprocessor communication protocol, particularly:

•

transfer of data between two modes of a multi-processor system with minimal host

CPU intervention,

•

execution of simple commands to provide basic features for system control

functions,

•

provision of fault tolerant features.

However, with disabling of features such as the protocol handling or with reduction of

the transmit rate (TSS901E automatically reduces transmit rate for sending null tokens)

also low power usage is supported.

Figure 1. TSS901E Block Diagram

Target applications are heterogeneous multi-processor systems supported by scalable

interfaces including the little/big endian swapping. The TSS901E connects modules with

different processors (e.g. TSC21020F, ERC32, TSC695E and others). Any kind of net-

work topology could be realized through the high speed point-to-point IEEE1355-links

(see chapter Applications).

Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIP-

SAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users

guide.

Receive

Transmit

macro

cell

Channel 2

RX1_DS

TX1_DS

RX2_DS

TX2_DS

Channel 1

JTAG

COMI

HOCI

PRCI

Test

CADR

CCTRL

CDATA

HADR

HCTRL

HDATA

HINT

RCPU

SES

UTIL

Protocol

Channel 3

RX3_DS

TX3_DS

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