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WM9713L Datasheet(PDF) 21 Page - Cirrus Logic |
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WM9713L Datasheet(HTML) 21 Page - Cirrus Logic |
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21 / 133 page ![]() WM9713L Rev 4.0 21 AC'97 MCLKA MCLKB 0 1 PCM PLL DIV 1-16 DIV 1-8 S EXT[3:0] / S PLL[3:0] / S EXT[6:4] / S PLL[6:4] / VOICE DAC HIFI DSP L/R ADCs L/R DACs AUX DAC WM9713L data bus clock VOICE DAC CLOCK AC97 CLK HIFI CLK CLK_MUX MUX 0 1 x2 x2 CLKBX2 CLKAX2 SYSCLK DIV 2 BCLK DIV 1-16 AUX ADC PENDIV [2:0] PCMCLK AC-Link Figure 10 Clocking Architecture for WM9713L INTERNAL CLOCK FREQUENCIES The internal clock frequencies are defined as follows (refer to Figure 10): AC97 CLK – nominally 24.576MHz, used to generate AC97 BITCLK at 12.288MHz HIFI CLK – for hi-fi playback at 48ks/s HIFI CLK = 24.576MHz. See Table 2 for voice only playback. Voice DAC CLK – see Table 2 for sample rate vs clock frequency. SAMPLE RATE VOICE DAC CLK FREQUENCY HIFI CLK FREQUENCY 8ks/s voice and hi-fi 2.048MHz 24.576MHz 8ks/s voice only (power save) 2.048MHz 4.096MHz 16ks/s voice and hi-fi 4.096MHz 24.576MHz 16ks/s voice only (power save) 4.096MHz 8.192MHz 32ks/s voice and hi-fi 8.192MHz 24.576MHz 48ks/s voice and hi-fi 12.288MHz 24.576MHz Table 2 Clock Division Mode Table |
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