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Data Sheet

AD9576

Rev. A | Page 21 of 65

Pin No.

Mnemonic

Input/

Output

Pin Type

Description

OUT10

Output

2.5 V/3.3 V CMOS,

1.8 V CMOS, HSTL,

LVDS, HCSL

Clock Output 10. When configured as 2.5 V/3.3 V CMOS, the logic high level is

determined by VDD_OUT10. The power-on format is determined via PPR1

(Pin 26). This pin is independently configurable via the serial port.

OUT10

Output

2.5 V/3.3 V CMOS,

1.8 V CMOS, HSTL,

LVDS, HCSL

Complimentary Clock Output 10. This pin is the complimentary signal to

the output on Pin 58 (OUT10).

VDD_VCO1

Input

Power

2.5 V or 3.3 V Power Supply.

VDD_PLL1

Input

Power

2.5 V or 3.3 V Power Supply.

LD_1

Output

2.5 V/3.3 V CMOS

PLL1 Lock Detector Status. Logic 0 means unlocked; Logic 1 means locked.

RESET

Input

Control

Reset. Logic 0 initializes the device to its default state (see the PPRx Pins

section for details). This pin has an internal 30 kΩ pull-up resistor.

VDD_REF2

Input

Power

2.5 V or 3.3 V Power Supply. Configure this supply to set the full swing

CMOS logic high level of Reference Input 2, REF2.

EPAD

Input

Ground

Exposed Pad. The exposed pad is a ground connection on the chip that

must be soldered to the analog ground of the PCB to ensure proper

functionality, heat dissipation, noise, and mechanical strength benefits.

AD9576 Datasheet(PDF) 21 Page - Analog Devices

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