AD9520-1SLASHPCBZ datasheet(74/80 Pages) AD

74 / 80 page

AD9520-1

Data Sheet

Rev. B | Page 74 of 80

Reg.

Addr.

(Hex) Bits

Name

Description

0x19A 7

Divider 3 bypass

Bypasses and powers down the divider; routes input to divider output.

0: uses divider (default).

1: bypasses divider.

Divider 3 ignore SYNC

Ignores SYNC.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

Divider 3 force high

Forces divider output to a specific state. This requires that ignore SYNC also be set. Note that

this bit has no effect if the channel divider is bypassed, but the driver polarity can still be reversed.

0: divider output is forced to low (default).

1: divider output is forced to the setting stored in Bit 4 of this register.

Divider 3 start high

Selects clock output to start high or start low.

0: starts low (default).

1: starts high.

[3:0]

Divider 3 phase offset

Phase offset (default: 0x0).

0x19B [7:3]

Unused

Unused.

Channel 3 power-down

Channel 3 powers down.

0: normal operation (default).

1: powered down. (Setting this bit puts OUT9/OUT9, OUT10/OUT10, and OUT11/OUT11 into

safe power-down mode.)

Channel 3 direct-to-output

Connects OUT9, OUT10, and OUT11 to Divider 3 or directly to VCO or CLK.

0: OUT9, OUT10, and OUT11 are connected to Divider 3 (default).

1: If Register 0x1E1[1:0] = 10b, the VCO is routed directly to OUT9, OUT10, and OUT11.

If Register 0x1E1[1:0] = 00b, the CLK is routed directly to OUT9, OUT10, and OUT11.

If Register 0x1E1[1:0] = 01b, there is no effect.

Disable Divider 3 DCC

Duty-cycle correction function.

0: enables duty-cycle correction (default); 1: disables duty-cycle correction.

Table 57. VCO Divider and CLK Input

Reg.

Addr.

(Hex) Bits

Name

Description

0x1E0 [2:0]

VCO divider

Bit 2

Bit 1

Bit 0

Divide

2 (default)

Output static

1 (bypass)

Output static

0x1E1 [7:5]

Unused

Unused.

Power down clock input

section

Powers down the clock input section (including CLK buffer, VCO divider, and CLK tree).

0: normal operation (default).

1: power-down.

Power down VCO clock

interface

Powers down the interface block between VCO and clock distribution.

0: normal operation (default).

1: power-down.

Power down VCO and CLK

Powers down both the VCO and the CLK input.

0: normal operation (default).

1: power-down.

Select VCO or CLK

Selects either the VCO or the CLK as the input to VCO divider.

0: selects external CLK as input to VCO divider (default).

1: selects VCO as input to VCO divider; VCO divider cannot be bypassed when this bit is set.

This bit must be set to use the PLL with the internal VCO.

Bypass VCO divider

Bypasses or uses the VCO divider.

0: uses VCO divider (default).

1: bypasses VCO divider; VCO cannot be selected as input when this bit is set.

AD9520-1/PCBZ Datasheet(PDF) 74 Page - Analog Devices

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