AD9739ABBCZ datasheet(54/64 Pages) AD

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AD9737A/AD9739A

Data Sheet

Rev. D | Page 54 of 64

For applications that do not have polling capabilities, the Mu

controller state machine should be reconfigured to restart the

search, such that lock can be re-attempted with system conditions

that may have changed and be different, and thus may enable

the controller to lock.

After the Mu delay value is found that exactly matches the desired

Mu phase setting and slope (for example, 6 with a negative slope),

the Mu controller goes into track mode. In this mode, the Mu

controller makes slight adjustments to the delay value to track any

variations between the two clock paths due to temperature, time,

and supply variations. Two status bits, MU_LKD (Register 0x2A,

Bit 0) and MU_LST (Register 0x2A, Bit 1) are available to the

user to signal the existing status control loop. If the current

phase is more than four steps away from the desired phase, the

MU_LKD bit is cleared, and if the lock acquired was previously

set, the MU_LST bit is set. Should the phase deviation return to

within three steps, the MU_LKD bit is set again while the MU_LST

is cleared. Note that this sort of event may occur if the main

clock input (that is, DACCLK) is disrupted or the Mu controller

exceeds the tapped delay line range (that is, <0 or >432).

If lock is lost, the Mu controller has the option of remaining in

the tracking loop or resetting and starting the search again via

the CONTRST bit (Register 0x29, Bit 5). Continued tracking is

the preferred state because it is the least disruptive to a system

in which the AD9737A/AD9739A temporarily loses lock. The

user can poll the Mu delay and phase value by first setting the

read bit high (Register 0x26, Bit 3). After the read bit is set, the

MUDEL[8:0] bits and the SET_PHS[4:0] bits (Register 0x27

and Register 0x28) that the controller is currently using can be

read.

INTERRUPT REQUESTS

The AD9737A/AD9739A can provide the host processor with

an interrupt request output signal (IRQ) that indicates that one

or more of the AD9737A/AD9739A internal controllers have

achieved lock or lost lock. These controllers include the Mu, data

receiver, and synchronization controllers. The host can then

poll the IRQ status register (Register 0x04) to determine which

controller has lost lock. The IRQ output signal is an active high

output signal available on Pin F13. If used, its output should be

connected via a 10 kΩ pull-up resistor to VDD33.

Each IRQ is enabled by setting the enable bits in Register 0x03,

which purposely has the same bit mapping as the IRQ status bits in

the controller transitions from a false to true state. Hence, it is

possible for the x_LCK_IRQ and x_LST_IRQ status bits to be set

when a controller temporarily loses lock but is able to reestablish

lock before the IRQ is serviced by the host. In this case, the host

should validate the present status of the suspect controller by

reading back its current status bits, which are available in

bits, the host can take appropriate action, if required, to

reestablish lock. To clear an IRQ after servicing, it is necessary

to reset relevant bits in Register 0x03 by writing 0 followed by

another write of 1 to reenable. A detailed diagram of the

interrupt circuitry is shown in Figure 168.

INT(n)

INT

SOURCE

SPI ISR

READ DATA

(PIN F13)

SPI WRITE

INT

SOURCE

SPI ADDRESS

DATA = 1

IMR

SCLK

SPI

DATA

Figure 168. Interrupt Request Circuitry

It is also possible to use the IRQ during the AD9737A/AD9739A

initialization phase after power-up to determine when the Mu

and data receiver controllers have achieved lock. For example,

before enabling the Mu controller, the MU_LCK_EN bit can be set

and the IRQ output signal monitored to determine when lock has

been established before continuing in a similar manner with the

data receiver controllers. Note that the relevant LCK bit should

be cleared before continuing to the next controller. After all

controllers are locked, the lost lock enable bits (that is,

x_LST_EN) should be set.

Table 28. Interrupt Request Registers

Address (Hex)

Bit

Description

0x03

MU_LST_EN

MU_LCK_EN

RCV_LST_EN

RCV_LCK_EN

0x04

MU_LST_IRQ

MU_LCK_IRQ

RCV_LST_IRQ

RCV_LCK_IRQ

0x21

RCVR_TRK_ON

RCVR_LST

RCVR_LCK

0x2A

MU_LST

MU_LKD

AD9739ABBCZ Datasheet(PDF) 54 Page - Analog Devices

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