AD9739ABBCZ datasheet(56/64 Pages) AD

56 / 64 page

AD9737A/AD9739A

Data Sheet

Rev. D | Page 56 of 64

CLOCK INPUT CONSIDERATIONS

VCC

VEE

VREF

Ω

Ω 50Ω

Ω

DACCLK_P

DACCLK_N

100

Ω

10nF

ADCLK914

AD9737A/AD9739A

10nF

Ω

Figure 173. ADCLK914 Interface to the AD9737A/AD9739A CLK Input

VCO

PLL

ADF4350

FREF

1.8V p-p

VVCO

1nF

3.9nH

RFOUTA–

RFOUTA+

RFOUTA–

RFOUTA+

100

Ω

DACCLK_P

DACCLK_N

DIV-BY-2N

N = 0 – 4

AD9737A/AD9739A

Figure 174. ADF4350 Interface to the AD9737A/AD9739A CLK Input

The quality of the clock source and its drive strength are important

considerations in maintaining the specified ac performance.

The phase noise and spur characteristics of the clock source

should be selected to meet the target application requirements.

For optimal ac performance of the AD9737A/AD9739A, the

recommended minimum differential peak-to-peak voltage is

approximately 1.4 VPP. Phase noise and spurs at a given

frequency offset on the clock source are directly translated to the

output signal. It can be shown that the phase noise characteristics

of a reconstructed output sine wave are related to the clock

source by 20 × log10(fOUT/fCLK) when the DAC clock path

contribution, along with thermal and quantization effects, are

negligible.

The AD9737A/AD9739A clock receiver provides optimum jitter

performance when driven by a fast slew rate originating from

the LVPECL or CML output drivers. For a low jitter sinusoidal

clock source, the ADCLK914 can be used to square-up the signal

and provide a CML input signal for the AD9737A/AD9739A

clock receiver. Note that all specifications and characterization

presented in the data sheet are with the ADCLK914 driven by a

high quality RF signal generator with the clock receiver biased at

an 800 mV level.

Figure 174 shows a clock source based on the ADF4350 low phase

noise/jitter PLL. The ADF4350 can provide output frequencies

from 140 MHz up to 4.4 GHz with jitter as low as 0.5 ps rms.

Each single-ended output can provide a squared-up output

level that can be varied from −4 dBm to +5 dBm, allowing for

>2 V p-p output differential swings. The ADF4350 also includes

an additional CML buffer that can be used to drive another

AD9737A/AD9739A device.

ESD

DACCLK_P

DACCLK_N

VDDC

VSSC

CLKx_OFFSET

DIR_x = 0

CLKx_OFFSET

DIR_x = 0

4-BIT PMOS

IOUT ARRAY

4-BIT NMOS

IOUT ARRAY

Figure 175. Clock Input and Common-Mode Control

AD9739ABBCZ Datasheet(PDF) 56 Page - Analog Devices

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