IC-MCB datasheet(21/28 Pages) ICHAUS

21 / 28 page

preliminary

iC-MCB

SPI-TO-BiSS BRIDGE WITH RS422 TRANSCEIVER

Rev A1, Page 21/28

Figure 13: Command via BiSS

BiSS register read

The register read access starts with CTO = 0x2. Within

the next four BiSS frames the host must read the reg-

ister address and the slave ID and determine if the

address is valid for access. The ID is also mapped to

the internal ID range. If reading of the current address is

allowed, the host sets the flag CVALID(0). Write access

to the current address is permitted with CVALID(1) and

the flag CVALID(2) is used to signalize write access to

the following address. With STB = 1 the register data

should be written to SPI address 0x4E and confirmed

with CVALID = 0x5. This can be done in a single SPI

frame. For auto increment access the same procedure

follows for the next bytes.

Figure 14: Register read via BiSS

BiSS register write

The write register access starts also with CTO = 0x2.

So setting the CVALID is the same procedure as for

read register. But after four BiSS frames CTO changes

to 0x3. With STB = 1 the data can be read from SPI

address 0x4E and must be confirmed with CVALID = 5.

This must be done in two SPI frames. Auto increment

access is also possible.

Figure 15: Register write via BiSS

IC-MCB Datasheet(PDF) 21 Page - IC-Haus GmbH