FS98O24 datasheet(21/77 Pages) FORTUNE

21 / 77 page

3.3.3. STATUS Register

The STATUS register contains the arithmetic status of ALU and the RESET status. The STATUS register is

similar to other registers, and can be the destination for any instruction. If the STATUS register is the

destination for an instruction that affects the Z or C bit, then the writing to these three bits is disabled. These

bits are set or cleared according to the device logic. The TO and PD bits are not writable.

property

R/W-0

U-X

R-0

U-X

R/W-X

STATUS

IRP1

IRP0

Bit7

Bit0

Bit 7

IRP1

: Indirect address 1 page select

1 = Indirect address 1 extend memory address is set (Memory 1XXH)

0 = Indirect address 1 extend memory address is Not set (Memory 0XXH)

Bit 6

IRP0

: Indirect address 0 page select

1 = Indirect address 0 extend memory address is set (Memory 1XXH)

0 = Indirect address 0 extend memory address is Not set (Memory 0XXH)

Bit 4

: Power down Flag.

1 = By execution of SLEEP instruction

0 = After power-on reset

Bit 3

: Watch Dog Time Out Flag. Cleared by writing 0 and Set by Watch Dog Time Out

1 = A Watch Dog Timer time-out occurred

0 = After power-on reset

Bit 1

: Carry Flag/borrow Flag (~Borrow)

(for borrow the polarity is reversed)

1 = If there is a carry out from the Most Significant bit of the result

0 = No carry out from the most significant bit of the result

Bit 0

: Zero Flag

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is NOT zero

property

R = Readable bit

W = Writable bit

U = unimplemented bit

- n = Value at Power On

reset

‘1’ = Bit is Set

‘0’ = Bit is Cleared

X = Bit is unknown

FS98O24 Datasheet(PDF) 21 Page - Fortune Semiconductor Corp.

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