RFM219SW

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User Registers

In the figure above, the raw data is the output of the demodulator. When the SNR of the incoming signal is very low, glitches

possibly exist on the raw data. The device will remove those glitches by internally sampling the raw data using the recovered

clock. The clean data is output to the DOUT. The sync clock is delayed by half cycle and output to the DCLK. The rising edge of

the output sync clock is centered on the output data. If the sync clock is turned off, the raw data will be directly output to the

DOUT.

The sync clock generator produces the clock according to the symbol rate configured on the RFPDK. It can tolerate a certain

amount of symbol rates offset existing between the real incoming signal and the symbol rate input on the RFPDK.. For more

details of the symbol rate offset tolerance, please refers to the “AN138 RFM219SW Configuration Guideline”.

5.9.2 Buffer Mode

In buffer mode, the data from the demodulator’s output are shifted into the 32 x 8-bit parallel FIFO after a valid sync word is

detected. The MCU can use the SPI to read the FIFO. The FIFO will retain its content and be readable in the STBY, TUNE and

RX state. The MCU can use the FIFO interrupts to assist to the FIFO reading. The optional preamble detection is supported.

EEPROM (Optional)

RF

DEMOD

clock

1

data

1

Preamble

(Optional)

Sync

(Must)

data

8

32 x 8-bit

FIFO

SPI

FCSB

CSB

SCL

SDA

User Registers

INT1

INT2

Figure 22. Data Path of Buffer Mode

Because the chip does all the data buffering work, the MCU can spend time on the other tasks during the buffering process. Also,

it reduces the MCU’s performance requirement in terms of speed and reactivity. The data receiving is independent of the

preamble detection, while the sync word detection is compulsory in the buffer mode.

5.9.3 Packet Mode

In packet mode, the data from the demodulator’s output are first shifted into the packet handler to get decoded, and then filled

into the 32 x 8-bit parallel FIFO.

EEPROM (Optional)

clock

RF

1

Packet

DEMOD

data

32 x 8-bit

SPI

FCSB

CSB

data

1

Handler

8

FIFO

SCL

SDA

INT1

INT2

Figure 23. Data Path of Packet Mode