ADP5072 datasheet(4/24 Pages) AD

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ADP5072

Data Sheet

Rev. 0 | Page 4 of 24

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INVERTING REGULATOR

Adjustable Negative Output Voltage

VNEG

−30

Reference Voltage

VREF

1.60

Reference Voltage Accuracy

−0.5

+0.5

TJ = 25°C

−1.5

+1.5

TJ = −40°C to +125°C

Feedback Voltage

VREF − VFB2

0.8

Feedback Voltage Accuracy

−0.5

+0.5

TJ = 25°C

−1.5

+1.5

TJ = −40°C to +125°C

Feedback Bias Current

IFB2

0.1

µA

Overvoltage Protection Threshold

VOV2

0.74

At FB2 pin after soft start

has completed

Load Regulation

(∆(VREF − VFB2)/(VREF − VFB2))/

ILOAD2

0.0004

%/mA

ILOAD2 = 5 mA to 75 mA

Line Regulation

(∆(VREF − VFB2)/(VREF − VFB2))/

VPVIN

0.003

%/V

VPVIN = 2.85 V to 5.5 V, ILOAD2 =

25 mA

EA Transconductance

gM2

260

300

340

µA/V

Power FET On Resistance

RDS (ON) INVERTER

350

mΩ

Power FET Maximum Drain Source

Voltage

VDS(MAX)INVERTER

Current-Limit Threshold, Main Switch

ILIM (INVERTER)

600

660

750

Minimum On Time

Minimum Off Time

SOFT START

Soft Start Timer for DC to DC Regulators

tSS

SS = open

SS resistor = 50 kΩ to GND

Hiccup Time

tHICCUP

8 × tSS

THERMAL SHUTDOWN

Threshold

TSHDN

150

°C

Hysteresis

THYS

°C

ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).

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