VSC8504-02 datasheet(31/131 Pages) MICROSEMI

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Functional Descriptions

VMDS-10507 VSC8504-02 Datasheet Revision 4.2

Figure 24 •

Inline Powered Ethernet Switch Diagram

The following procedure describes the process that an Ethernet switch must perform to process inline

power requests made by a link partner (LP) that is, in turn, capable of receiving inline power:

Enable the inline powered device detection mode on each VSC8504-02 PHY using its serial

management interface. Set register bit 23E1.10 to 1.

Ensure that the VSC8504-02 autonegotiation enable bit (register 0.12) is also set to 1. In the

application, the device sends a special fast link pulse (FLP) signal to the LP. Reading register

bit 23E1.9:8 returns 00 during the search for devices that require power over Ethernet (PoE).

The VSC8504-02 PHY monitors its inputs for the FLP signal looped back by the LP. An LP capable

of receiving PoE loops back the FLP pulses when the LP is in a powered down state. This is

reported when VSC8504-02 register bit 23E1.9:8 reads back 01. It can also be verified as an inline

power detection interrupt by reading VSC8504-02 register bit 26.9, which should be a 1, and which

is subsequently cleared and the interrupt de-asserted after the read. When an LP device does not

loop back the FLP after a specific time, VSC8504-02 register bit 23E1.9:8 automatically resets to 10.

If the VSC8504-02 PHY reports that the LP requires PoE, the Ethernet switch must enable inline

power on this port, externally of the PHY.

The PHY automatically disables inline powered device detection when the VSC8504-02 register bits

23E1.9:8 automatically reset to 10, and then automatically changes to its normal autonegotiation

process. A link is then autonegotiated and established when the link status bit is set (register bit 1.2

is set to 1).

In the event of a link failure (indicated when VSC8504-02 register bit 1.2 reads 0), it is

recommended that the inline power be disabled to the inline powered device external to the PHY.

The VSC8504-02 PHY disables its normal autonegotiation process and re-enables its inline

powered device detection mode.

SMI

Control

Processor

PHY_port1

QSGMII/

SGMII

Interface

Inline,

Power-Over-Ethernet

(PoE)

Power Supply

Cat5

Gigabit Switch

PHY_port0

PHY_portn

Transformer

RJ-45

I/F

Transformer

RJ-45

I/F

Transformer

RJ-45

I/F

Link

Partner

Link

Partner

Link

Partner

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