 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
VSC8504-02 Datasheet(PDF) 69 Page - Microsemi Corporation |
|
|
|||||||||||||||||||||||||||||
VSC8504-02 Datasheet(HTML) 69 Page - Microsemi Corporation |
|
|
69 / 131 page  Registers VMDS-10507 VSC8504-02 Datasheet Revision 4.2 58 4.2.24 Interrupt Status The status of interrupts already written to the device is available for reading from register 26 in the main registers space. The following table shows the expected readouts. The following information applies to the interrupt status bits: • All set bits in this register are cleared after being read (self-clearing). If bit 26.15 is set, the cause of the interrupt can be read by reading bits 26.14:0. • For bits 26.14 and 26.12, bit 0.12 must be set for this interrupt to assert. • For bit 26.2, bits 4.8:5 must be set for this interrupt to assert. • For bit 26.0, this interrupt will not occur when RX_ER is used for carrier-extension decoding of a link partner's data transmission. 4.2.25 Device Auxiliary Control and Status Register 28 provides control and status information for several device functions not controlled or monitored by other device registers. The following table shows the settings available and the expected readouts. Table 42 • Interrupt Status, Address 26 (0x1A) Bit Name Access Description Default 15 Interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 14 Speed state change status RO Self-clearing bit. 1: Interrupt pending. 0 13 Link state change status RO Self-clearing bit. 1: Interrupt pending. 0 12 FDX state change status RO Self-clearing bit. 1: Interrupt pending. 0 11 Autonegotiation error status RO Self-clearing bit. 1: Interrupt pending. 0 10 Autonegotiation complete status RO Self-clearing bit. 1: Interrupt pending. 0 9 Inline powered device detect status RO Self-clearing bit. 1: Interrupt pending. 0 8 Symbol error status RO Self-clearing bit. 1: Interrupt pending. 0 7 Fast link failure detect status RO Self-clearing bit. 1: Interrupt pending. 0 6:5 Reserved RO 0 4 AMS media changed mask(1) 1. If hardware interrupts are not used, the mask can still be set and the status polled for changes. RO Self-clearing bit. 1: Interrupt pending. 0 3 False carrier interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 2 Link speed downshift detect status RO Self-clearing bit. 1: Interrupt pending. 0 1 Master/Slave resolution error status RO Self-clearing bit. 1: Interrupt pending. 0 0 RX_ER interrupt status RO Self-clearing bit. 1: Interrupt pending. 0 Table 43 • Auxiliary Control and Status, Address 28 (0x1C) Bit Name Access Description Default 15 Autonegotiation complete RO Duplicate of bit 1.5 0 14 Autonegotiation disabled RO Inverted duplicate of bit 0.12 0 131 HP Auto-MDIX crossover indication RO 1: HP Auto-MDIX crossover performed internally 0 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
British ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
