LFEC datasheet(29/117 Pages) LATTICE

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2-26

Architecture

Lattice Semiconductor

LatticeECP/EC Family Data Sheet

Figure 2-30. Tristate Register Block

Control Logic Block

The control logic block allows the selection and modiﬁcation of control signals for use in the PIO block. A clock is

selected from one of the clock signals provided from the general purpose routing and a DQS signal provided from

the programmable DQS pin. The clock can optionally be inverted.

The clock enable and local reset signals are selected from the routing and optionally inverted. The global tristate

signal is passed through this block.

DDR Memory Support

Implementing high performance DDR memory interfaces requires dedicated DDR register structures in the input

(for read operations) and in the output (for write operations). As indicated in the PIO Logic section, the EC devices

provide this capability. In addition to these registers, the EC devices contain two elements to simplify the design of

input structures for read operations: the DQS delay block and polarity control logic.

DLL Calibrated DQS Delay Block

Source Synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at

the input register. For most interfaces a PLL is used for this adjustment, however in DDR memories the clock

(referred to as DQS) is not free running so this approach cannot be used. The DQS Delay block provides the

required clock alignment for DDR memory interfaces.

The DQS signal (selected PIOs only) feeds from the PAD through a DQS delay element to a dedicated DQS rout-

ing resource. The DQS signal also feeds polarity control logic which controls the polarity of the clock to the sync

registers in the input register blocks. Figures 2-31 and 2-32 show how the DQS transition signals are routed to the

PIOs.

The temperature, voltage and process variations of the DQS delay block are compensated by a set of calibration

(6-bit bus) signals from two DLLs on opposite sides of the device. Each DLL compensates DQS Delays in its half of

the device as shown in Figure 2-32. The DLL loop is compensated for temperature, voltage and process variations

by the system clock and feedback loop.

LE*

D-Type

ONEG1

CLK1

Programmed

Control

Latch

*Latch is transparent when input is low.

OPOS1

OUTDDN

/LATCH

From

Routing

To sysIO

Buffer

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