Data Sheet AS8446

Revision 1.8, Date 2005-03-17

Page 23 of 35

Communication Protocol

The Three-Wire Interface -interface acts as communication interface between the µP or PC and the registers within the AS8446.

For efficient register access, a protocol has been defined with the following features:

Purely master-slave protocol with µP or PC as master

Two different frames: One read and one write frame

Frame is delimited by the status of CS (CS = frame delimiter or chip select signal), one frame consists of 16 Bits (header byte

and data byte).

Special remark for interface lock condition: If a frame does not consist of 16 bits (can be caused e.g. by spiking, noise or

interrupt), the interface will be locked. In order to leave this lock situation CS = high and one or several clock pulses must be

set. Setting CS = high alone will not be sufficient.

Referring to Figure 10 and Figure 11, a Clk pulse with CS = high must be set in order to reset the interface and to ensure a safe

communication.

Data Fields

HEADER H

MSB

H

LSB

R/W

-

-

A4A3A2

A1A0

A4, A3, A2, A1, A0: Address A (Register address to read or to write)

R/W = MSB, A0 = LSB.

R/W: Read or Write

R/W =0: Read (Data are read/transmitted from the AS8446 via the DATAout pin.)

R/W =1: Write (Data are write/transmitted from the µP or PC to the AS8446 via the DATAin pin.)

DATA D

MSB

D

LSB

D7

D6

D5

D4

D3

D2

D1

D0

D7…D0: Data (Denotes the data of the register addressed. D7=MSB, D0=LSB)

Note:

To ensure a correct register setting the use of µP based verification (Write, Read-Back, Verify) is mandatory.