STM8S datasheet(267/467 Pages) STMICROELECTRONICS

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RM0016

Serial peripheral interface (SPI)

287

20.3.2

Configuring the SPI in slave mode

In slave configuration, the serial clock is received on the SCK pin from the master device.

The value set in the BR[2:0] bits in the SPI_CR1 register, does not affect the data transfer

rate.

Follow the procedure below to configure the SPI in slave mode:

Select the CPOL and CPHA bits to define one of the four relationships between the

data transfer and the serial clock (see Figure 93). For correct data transfer, the CPOL

and CPHA bits must be configured in the same way in the slave device and the master

device.

The frame format (MSB-first or LSB-first depending on the value of the LSBFIRST bit in

the SPI_CR1 register) must be the same as the master device.

In Hardware mode (refer to Slave select (NSS) pin management on page 264), the

NSS pin must be connected to a low level signal during the complete data transmit

sequence. In NSS Software mode, set the SSM bit and clear the SSI bit in the

SPI_CR2 register.

Clear the MSTR bit and set the SPE bit to assign the pins to alternate functions.

In this configuration the MOSI pin is a data input and the MISO pin is a data output.

Note:

In applications with a parallel multi-slave structure, with separate NSS signals and the slave

MISO outputs connected together, the corresponding GPIO registers must be configured

correctly. The SPI_MISO pin is controlled by the SPI peripheral only when the NSS signal is

active and the device is selected as slave. When the NSS signal is released, the pin is

driven by GPIO register settings only. To function correctly, the GPIO has to be configured in

input pull-up mode with no interrupt. This configuration is done using the GPIO_DDR,

GPIO_CR1 and GPIO_CR2 registers - see Section 11.8.1: Alternate function output.

20.3.3

Configuring the SPI master mode

In a master configuration, the serial clock is generated on the SCK pin.

Follow the procedure below to configure the SPI in master mode:

Select the BR[2:0] bits to define the serial clock baud rate (see SPI_CR1 register).

Select the CPOL and CPHA bits to define one of the four relationships between the

data transfer and the serial clock (see Figure 93).

Configure the LSBFIRST bit in the SPI_CR1 register to define the frame format.

In Hardware mode, connect the NSS pin to a high-level signal during the complete data

transmit sequence. In software mode, set the SSM and SSI bits in the SPI_CR2

Set the MSTR and SPE bits (they remain set only if the NSS pin is connected to a high-

level signal).

In this configuration the MOSI pin is a data output and to the MISO pin is a data input.

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