STM8S datasheet(268/467 Pages) STMICROELECTRONICS

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Serial peripheral interface (SPI)

RM0016

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DocID14587 Rev 14

20.3.4

Configuring the SPI for simplex communications

The SPI is capable of operating in simplex mode in 2 configurations.

•

1 clock and 1 bidirectional data wire

•

1 clock and 1 data wire (Receive-only or Transmit-only)

1 clock and 1 bidirectional data wire

This mode is enabled by setting the BDM bit in the SPI_CR2 register. In this mode SCK is

used for the clock, and MOSI in master or MISO in slave mode is used for data

communication. The transfer direction (Input/output) is selected by the BDOE bit in the

SPI_CR2 register. When this bit is set to 1, the data line is output, otherwise it is input.

1 clock and 1 unidirectional data wire (BDM = 0)

In this mode, the application can use the SPI either in transmit-only mode or in receive-only

mode:

•

Transmit-only mode is similar to full-duplex mode (BDM = 0, RXONLY = 0): the data is

transmitted to the transmit pin (MOSI in master mode or MISO in slave mode) and the

receive pin (MISO in master mode or MOSI in slave mode) can be used as general

purpose I/O. In this case, the application just needs to ignore the Rx buffer (if the data

•

In receive-only mode, the application can disable the SPI output function by setting the

RXONLY bit in the SPI_CR2 register. In this case, it frees the transmit I/O pin (MOSI in

master mode or MISO in slave mode) so it can be used for other purposes.

To start the communication in receive-only mode, configure and enable the SPI:

•

In master mode, the communication starts immediately and stops when the SPE bit is

reset and the current reception stops. There is no need to read the BSY flag in this

mode. It is always set when an SPI communication is ongoing.

•

In slave mode, the SPI continues to receive as long as the NSS is pulled down (or the

SSI bit is reset in NSS software mode) and the SCK is running.

20.3.5

Data transmission and reception procedures

Rx and Tx buffer

In reception, data are received and then stored into an internal Rx buffer while In

transmission, data are first stored into an internal Tx buffer before being transmitted.

A read access of the SPI_DR register returns the Rx buffered value whereas a write access

of the SPI_DR stores the written data into the Tx buffer.

Start sequence in master mode

•

In full-duplex (BDM = 0 and RXONLY = 0)

–

The sequence begins when data is written into the SPI_DR register (Tx buffer).

–

The data is then parallel loaded from the Tx buffer into the 8-bit shift register

during the first bit transmission and then shifted out serially to the MOSI pin.

–

At the same time, the received data on MISO pin is shifted in serially to the 8-bit

shift register and then parallel loaded into the SPI_DR register (Rx Buffer).

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