STM8S datasheet(278/467 Pages) STMICROELECTRONICS

278 / 467 page

Serial peripheral interface (SPI)

RM0016

278/467

DocID14587 Rev 14

To avoid any of these effects, it is recommended to respect the following procedure when

disabling the SPI:

In master or slave full duplex mode (BDM = 0, RXONLY = 0):

Wait until RXNE = 1 to receive the last data

Wait until TXE = 1

Then wait until BSY = 0

Disable the SPI (SPE = 0) and eventually enter Halt mode (or disable the peripheral

clock).

In master or slave unidirectional transmit-only mode (BDM = 0, RXONLY = 0)

or bidirectional transmit mode (BDM = 1, BDOE = 1):

After the last data is written in the SPI_DR register:

Wait until TXE = 1

Then wait until BSY = 0

Disable the SPI (SPE = 0) and, if desired, enter Halt mode (or disable the peripheral

clock).

In master unidirectional receive-only mode (MSTR = 1, BDM = 0, RXONLY = 1)

or bidirectional receive mode (MSTR = 1, BDM = 1, BDOE = 0):

This case must be managed in a particular way to ensure that the SPI does not initiate a

new transfer:

Wait for the second to last occurrence of RXNE = 1 (n-1)

Then wait for one SPI clock cycle (using a software loop) before disabling the SPI

(SPE = 0)

Then wait for the last RXNE=1 before entering Halt mode (or disabling the peripheral

clock).

Note:

In master bidirectional receive mode (MSTR=1 and BDM=1 and BDOE=0), the BSY flag is

kept low during a transfer.

In slave receive-only mode (MSTR = 0, BDM = 0, RXONLY = 1) or bidirectional

receive mode (MSTR = 0, BDM = 1, BDOE = 0):

You can disable the SPI (write SPE = 1) whenever you want: the current transfer will

complete before being effectively disabled.

Then, if you want to enter Halt mode, you must first wait until BSY = 0 before entering

Halt mode (or disabling the peripheral clock).

STM8S Datasheet(PDF) 278 Page - STMicroelectronics