STM8S datasheet(279/467 Pages) STMICROELECTRONICS

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RM0016

Serial peripheral interface (SPI)

287

20.3.9

Error flags

Master mode fault (MODF)

Master mode fault occurs when the master device has its NSS pin pulled low (in NSS

hardware mode) or SSI bit low (in NSS software mode), this automatically sets the MODF

bit. Master mode fault affects the SPI peripheral in the following ways:

•

The MODF bit is set and an SPI interrupt is generated if the ERRIE bit is set.

•

The SPE bit is reset. This blocks all output from the device and disables the SPI

interface.

•

The MSTR bit is reset, thus forcing the device into slave mode.

Use the following software sequence to clear the MODF bit:

Make a read or write access to the SPI_SR register while the MODF bit is set.

Then write to the SPI_CR1 register.

To avoid any multiple slave conflicts in a system comprising several MCUs, the NSS pin

must be pulled high during the MODF bit clearing sequence. The SPE and MSTR bits can

be restored to their original state after this clearing sequence.

As a security, hardware does not allow you to set the SPE and MSTR bits while the MODF

bit is set.

In a slave device the MODF bit cannot be set. However, in a multi-master configuration, the

device can be in slave mode with this MODF bit set. In this case, the MODF bit indicates

that there might have been a multimaster conflict for system control. You can use an

interrupt routine to recover cleanly from this state by performing a reset or returning to a

default state.

Overrun condition

An overrun condition occurs, when the master device has sent data bytes and the slave

device has not cleared the RXNE bit resulting from the previous data byte transmitted.

When an overrun condition occurs:

•

OVR bit is set and an interrupt is generated if the ERRIE bit is set.

In this case, the receiver buffer contents will not be updated with the newly received data

from the master device. A read to the SPI_DR register returns this byte. All other

subsequently transmitted bytes are lost.

Clearing the OVR bit is done by a read access to the SPI_DR register followed by a read

access to the SPI_SR register.

CRC error

This flag is used to verify the correctness of the value received when the CRCEN bit in the

SPI_CR2 register is set. The CRCERR flag in the SPI_SR register is set if the value

received in the shift register after the SPI_TXCRCR value transmission does not match the

SPI_RXCRCR value. Refer to Chapter 20.3.6: CRC calculation.

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