STM8S datasheet(283/467 Pages) STMICROELECTRONICS

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RM0016

Serial peripheral interface (SPI)

287

20.4.2

SPI control register 2 (SPI_CR2)

Address offset: 0x01

Reset value: 0x00

654

3210

BDM

BDOE

CRCEN

CRCNEXT

Reserved

RXOnly

SSM

SSI

Bit 7 BDM: Bidirectional data mode enable

0: 2-line unidirectional data mode selected

1: 1-line bidirectional data mode selected

Bit 6 BDOE: Input/Output enable in bidirectional mode

This bit selects the direction of transfer in bidirectional mode when BDM is set to 1.

0: Input enabled (receive-only mode)

1: Output enabled (transmit-only mode)

In master mode, the MOSI pin is used and in slave mode, the MISO pin is used.

Bit 5 CRCEN: Hardware CRC calculation enable

0: CRC calculation disabled

1: CRC calculation Enabled

Note: This bit should be written only when SPI is disabled (SPE = ‘0’) for correct operation

Bit 4 CRCNEXT: Transmit CRC next

0: Next transmit value is from Tx buffer

1: Next transmit value is from Tx CRC register

Bit 3 Reserved

Bit 2 RXONLY: Receive only

0: Full duplex (Transmit and receive)

1: Output disabled (Receive only mode)

This bit combined with BDM bit selects the direction of transfer in 2 line uni-directional mode

This bit is also useful in a multi-slave system in which this particular slave is not accessed, the output

from the accessed slave is not corrupted.

Bit 1 SSM: Software slave management

0: Software slave management disabled

1: Software slave management enabled

When the SSM bit is set, the NSS pin input is replaced with the value coming from the SSI bit

Bit 0 SSI: Internal slave select

This bit has effect only when SSM bit is set. The value of this bit is forced onto the NSS pin and the I/O

value of the NSS pin is ignored.

0: Slave mode

1: Master mode

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