STM8S datasheet(397/467 Pages) STMICROELECTRONICS

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RM0016

Controller area network (beCAN)

427

23.6.6

Bit timing

The bit timing logic monitors the serial bus-line and performs sampling and adjustment of

the sample point by synchronizing on the start-bit edge and resynchronizing on the following

edges. Its operation may be explained simply by splitting nominal bit time into three

segments as follows:

–

Synchronization segment (SYNC_SEG): a bit change is expected to occur

within this time segment. It has a fixed length of one time quantum (1 x tCAN).

–

Bit segment 1 (BS1): defines the location of the sample point. It includes the

PROP_SEG and PHASE_SEG1 of the CAN standard. Its duration is

programmable between 1 and 16 time quanta but may be automatically

lengthened to compensate for positive phase drifts due to differences in the

frequency of the various nodes of the network.

–

Bit segment 2 (BS2): defines the location of the transmit point. It represents the

PHASE_SEG2 of the CAN standard. Its duration is programmable between 1 and

8 time quanta but may also be automatically shortened to compensate for

negative phase drifts.

The resynchronization Jump Width (SJW) defines an upper bound to the amount of

lengthening or shortening of the bit segments. It is programmable between 1 and 4 time

quanta.

To guarantee the correct behavior of the CAN controller, SYNC_SEG + BS1 + BS2 must be

greater than or equal to 5 time quanta.

Note:

For a detailed description of the CAN bit timing and resynchronization mechanism, please

refer to the ISO 11898 standard.

As a safeguard against programming errors, the configuration of the Bit Timing Registers

CAN_BTR1 and CAN_BTR2 is only possible while the device is in Initialization mode.

Figure 154. Bit timing

with

where tq refers to the time quantum, tsys is the system clock period (fMASTER). BRP[5:0],

BS1[3:0], and BS2[2:0] are defined in the CAN_BTR1 and CAN_BTR2 registers.

BaudRate

NominalBitTime

----------------------------------------------

NominalBitTime

tq tBS1 tBS2

tBS1

BS1[3:0] 1

() tq

tBS2

BS2[2:0] 1

() tq

BRP[5:0] 1

() tsys

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