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STM8S Datasheet(PDF) 400 Page - STMicroelectronics |
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STM8S Datasheet(HTML) 400 Page - STMicroelectronics |
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400 / 467 page ![]() Controller area network (beCAN) RM0016 400/467 DocID14587 Rev 14 23.8 Register access protection Erroneous access to certain configuration registers can cause the hardware to temporarily disturb the whole CAN network. Therefore the following registers can be modified by software only while the hardware is in initialization mode: CAN_BTR1, CAN_BTR2, CAN_FCR1, CAN_FCR2, CAN_FMR1, CAN_FMR2 and CAN_DGR registers. Although the transmission of incorrect data will not cause problems at the CAN network level, it can severely disturb the application. A transmit mailbox can be only modified by software while it is in empty state, refer to Figure 146: Transmit mailbox states. The filters must be deactivated before their value can be modified by software. The modification of the filter configuration (scale or mode) can be done by software only in initialization mode. 23.9 Clock system The clock tolerance limit as specified in CAN protocol is 1.58 % at speeds of up to 125 Kbps. For higher baud rates, it is suggested to use a crystal oscillator. Note: If the clock security system feature is enabled in the CLK controller (Refer to the description of the CSSEN bit in the Clock security system register (CLK_CSSR) on page 97), there is a way to put CAN automatically into the recessive state when a main clock failure occurs, so that the CAN network does not get stuck by the device. However to ensure this, the PG0 I/O pin must be configured in pull-up mode prior to using the beCAN. In this way, when a failure occurs and the I/O alternate function is disabled, the line is pulled-up instead of floating. 23.10 beCAN low power modes Note: If a CAN frame is received in Wait, Halt or Active-halt modes, the microcontroller will be woken-up but the CAN frame will be lost. Table 68. beCAN behavior in low power modes Mode Description Wait No effect on beCAN, except that accesses to Tx/Rx mailboxes and filter values are not possible (CPU clock is stopped). beCAN interrupts cause the device to exit from WAIT mode. Slow No effect on beCAN. Halt/ Active- halt BeCAN is halted. If the beCAN has been successfully put in Sleep mode (refer to Section 23.4.3) before executing the halt instruction, any falling edge detected on CAN_RX pin will trigger a beCAN Rx interrupt and wake-up the device from Halt/Active-halt mode. |
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