STM8S datasheet(404/467 Pages) STMICROELECTRONICS

404 / 467 page

Controller area network (beCAN)

RM0016

404/467

DocID14587 Rev 14

23.11.4

CAN transmit priority register (CAN_TPR)

Address offset: 0x03

Reset value: 0x0C

Bit 2 RQCP2 Request Completed for Mailbox 2

This bit is set by hardware to signal that the last request for mailbox 2 has been completed. The

request could be a transmit or an abort request.

This bit is cleared by software writing 1.

Bit 1 RQCP1 Request Completed for Mailbox 1

This bit is set by hardware to signal that the last request for mailbox 1 has been completed. The

request could be a transmit or an abort request.

This bit is cleared by software writing 1.

Bit 0 RQCP0 Request Completed for Mailbox 0

This bit is set by hardware to signal that the last request for mailbox 0 has been completed. The

request could be a transmit or an abort request.

This bit is cleared by software writing 1.

654

3210

LOW2

LOW1

LOW0

TME2

TME1

TME0

CODE1

CODE0

rrr

rrrr

Bit 7 LOW2 Lowest Priority Flag for Mailbox 2

This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 2

has the lowest priority.

Note: It is set to zero when only one mailbox is pending.

Bit 6 LOW1 Lowest Priority Flag for Mailbox 1

This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 1

has the lowest priority.

Note: It is set to zero when only one mailbox is pending.

Bit 5 LOW0 Lowest Priority Flag for Mailbox 0

This bit is set by hardware when more than one mailbox is pending for transmission and mailbox 0

has the lowest priority.

Note: It is set to zero when only one mailbox is pending.

Bit 4 TME2 Transmit Mailbox 2 Empty

This bit is set by hardware when no transmit request is pending for mailbox 2.

Note: This bit is reserved, forced to 0 by hardware in ST7 beCAN compatibility mode (TXM2E bit = 0

in CAN_DGR register).

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