UPD360 datasheet(66/221 Pages) MICROCHIP

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UPD360

DS00002084C-page 66

 2016-2017 Microchip Technology Inc.

8.5.43

GENERAL PURPOSE TIMER INTERRUPT SOURCE REGISTER (GP_TIMER_INT_SRC)

8.5.44

GENERAL PURPOSE TIMER CONTROL REGISTER (GP_TIMER_CTL)

Address:

00A2h

Size:

8 bits

BITS

DESCRIPTION

TYPE

DEFAULT

7:1

RESERVED

GP_UFLOW

This bit will be set when the general purpose timer underflows. The

GP_TIMER_INT interrupt in Interrupt Status Register (INT_STS) persists

until this bit is cleared.

When DIS_ON_UFLOW bit of the General Purpose Timer Control Register

(GP_TIMER_CTL) is set, the assertion of this bit is delayed until the timer is

fully disabled (100s us).

R/WC

Address:

00A3h

Size:

8 bits

BITS

DESCRIPTION

TYPE

DEFAULT

STATUS

This bit indicates the operational state of the GP timer.

0: Timer is disabled and not counting

1: Timer is enabled and counting

When this bit is cleared the timer has halted operation.

6:3

RESERVED

DIS_ON_UFLOW

When this bit is set, the GP timer is automatically disabled upon detection

of the underflow condition. Additionally, the ENABLE bit is cleared upon

underflow detection and the assertion of GP_UFLOW will be delayed until

the GP Timer has halted operation and the STATUS bit is cleared.

R/W

RESET

Timer Reset. When set this bit stops the timer and resets the internal counter

to the value in the General Purpose Timer Load Register

(GP_TIMER_LOAD).

0: Timer is not in reset

1: Timer is in reset

Note:

This bit does not clear until propagation of the reset completes.

This may take 100s us.

R/SC

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