ASM2I99448 datasheet(11/15 Pages) ALSC

11 / 15 page

May 2005

ASM2I99448

rev 0.3

3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer

11 of 15

Notice: The information in this document is subject to change without notice.

PCLK

VPP

VCMR

VCC

VCC ÷2

GND

tP(LH)

tP(HL)

CCLK

VCC

VCC ÷2

GND

tP(LH)

tP(HL)

VCC

VCC ÷2

GND

tSK(LH)

tSK(HL)

VCC

VCC ÷2

GND

VCC

VCC ÷2

GND

The pin-to-pin skew is defined as the worst case

difference in propagation between any similar delay path

within a single device

CCLK

VCC

VCC ÷2

GND

tP(LH)

tP(HL)

VCC

VCC ÷2

GND

tSK(P) =| tPHL - tPHL |

VCC

VCC ÷2

GND

DC (tP ÷T0 Χ 100%)

The time from the output controlled edge to the

non-controlled edge, divided by the time output

controlled edge, expressed as a percentage.

VCC = 3.3V VCC = 2.5V

2.4

1.8V

0.5

0.6V

TN + 1

TJIT(CC) = |TN -TN + 1|

The variation in cycle time of a single between adjacent

cycles, over a random sample of adjacent cycle pairs

CCLK

PCLK

VCC

VCC ÷2

GND

VCC

VCC ÷2

GND

CLK_STOP

Figure 11. Propagation Delay (tPD) Test Reference

Figure 12. Propagation Delay (tPD) Test Reference

Figure 13. Output–to–Output Skew tSK(LH, HL)

Figure 14. Output Pulse Skew (tSK(P) Test Reference

Figure 16. Output Transition Time Test Reference

Figure 15. Output Duty Cycle (DC)

Figure 17. Cycle–to–Cycle Jitter Reference

Figure 18. Setup and Hold Time (tS, tH) Test

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