STM32F722IC datasheet(23/229 Pages) STMICROELECTRONICS

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DS11853 Rev 6

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STM32F722xx STM32F723xx

Functional overview

3.3

Embedded Flash memory

The STM32F722xx and STM32F723xx devices embed a Flash memory of up to 512 Kbytes

available for storing programs and data.

The flexible protections can be configured thanks to option bytes:

•

Readout protection (RDP) to protect the whole memory. Three levels are available:

–

Level 0: no readout protection

–

Level 1: No access (read, erase, program) to the Flash memory or backup SRAM

can be performed while the debug feature is connected or while booting from RAM

or system memory bootloader

–

Level 2: debug/chip read protection disabled.

•

Write protection (WRP): the protected area is protected against erasing and

programming.

•

Proprietary code readout protection (PCROP): Flash memory user sectors (0 to 7) can

be protected against D-bus read accesses by using the proprietary readout protection

(PCROP). The protected area is execute-only.

3.4

CRC (cyclic redundancy check) calculation unit

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link-

time and stored at a given memory location.

3.5

Embedded SRAM

All the devices feature:

•

System SRAM up to 256 Kbytes:

–

SRAM1 on AHB bus Matrix: 176 Kbytes

–

SRAM2 on AHB bus Matrix: 16 Kbytes

–

DTCM-RAM on TCM interface (Tighly Coupled Memory interface): 64 Kbytes for

critical real-time data.

•

Instruction RAM (ITCM-RAM) 16 Kbytes:

–

It is mapped on TCM interface and reserved only for CPU Execution/Instruction

useful for critical real-time routines.

The Data TCM RAM is accessible by the GP-DMAs and peripheral DMAs through the

specific AHB slave of the CPU.The instruction TCM RAM is reserved only for CPU. It is

accessed at CPU clock speed with 0 wait states.

•

4 Kbytes of backup SRAM

This area is accessible only from the CPU. Its content is protected against possible

unwanted write accesses, and is retained in Standby or VBAT mode.

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