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STM32F722IC Datasheet(PDF) 35 Page - STMicroelectronics |
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STM32F722IC Datasheet(HTML) 35 Page - STMicroelectronics |
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35 / 229 page ![]() DS11853 Rev 6 35/229 STM32F722xx STM32F723xx Functional overview 49 Figure 13. Startup in regulator OFF: slow VDD slope - power-down reset risen after VCAP_1/VCAP_2 stabilization 1. This figure is valid whatever the internal reset mode (ON or OFF). Figure 14. Startup in regulator OFF mode: fast VDD slope - power-down reset risen before VCAP_1/VCAP_2 stabilization 1. This figure is valid whatever the internal reset mode (ON or OFF). ai18491f VDD time Min V12 PDR = 1.7 V or 1.8 V VCAP_1 / VCAP_2 V12 NRST time VDD time Min V12 VCAP_1 / VCAP_2 V12 PA0 asserted externally NRST time ai18492e PDR = 1.7 V or 1.8 V |
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