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ASM5I9350 Datasheet(PDF) 2 Page - Alliance Semiconductor Corporation |
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ASM5I9350 Datasheet(HTML) 2 Page - Alliance Semiconductor Corporation |
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2 / 12 page  July 2005 ASM5I9350 rev 0.2 3.3V 1:10 LVCMOS PLL Clock Generator 2 of 12 Notice: The information in this document is subject to change without notice. Block Diagram Pin Configuration SELA QD0 QD1 QD2 QD3 QD4 QC0 QC1 +4/ +8 +4/ +8 VCO 200-500MHz Phase Detector LPF XIN XOUT FB_SEL SELB SELD OE# +16/+32 +4/ +8 QB +2/ +4 QA osc PLL_EN REF_SEL TCLK SELC 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 FB_SEL SELA SELB SELC SELD AVSS XOUT AVDD VDDQD QD0 VSS QC1 VDDQC QC0 QD1 VSS ASM5I9350 |
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