ASM5I9350 datasheet(7/12 Pages) ALSC

7 / 12 page

July 2005

ASM5I9350

rev 0.2

3.3V 1:10 LVCMOS PLL Clock Generator

7 of 12

Notice: The information in this document is subject to change without notice.

AC Electrical Specifications (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1

Parameter

Description

Condition

Min

Typ

Max

Unit

fVCO

VCO Frequency

200

500

MHz

÷16 Feedback

12.5

31.25

÷32 Feedback

6.25

15.625

fin

Input Frequency

Bypass mode

(PLL_EN = 0)

200

MHz

fXTAL

Crystal Oscillator Frequency

MHz

frefDC

Input Duty Cycle

tr, tf

TCLK Input Rise/FallTime

0.8V to 2.0V

1.0

÷2 Output

100

200

÷4 Output

125

fMAX

Maximum Output Frequency

÷8 Output

62.5

MHz

fMAX < 100 MHz

47.5

52.5

Output Duty Cycle

fMAX > 100 MHz

tr, tf

Output Rise/Fall times

0.8V to 2.4V

0.1

1.0

tsk(O)

Output-to-Output Skew

Banks at same voltage

150

tsk(B)

Bank-to-Bank Skew

Banks at different voltages

350

tPLZ, HZ

Output Disable Time

tPZL, ZH

Output Enable Time

÷16 Feedback

0.7 – 0.9

PLL Closed Loop Bandwidth (–3dB)

÷32 Feedback

0.6 – 0.8

MHz

Same frequency

150

tJIT(CC)

Cycle-to-Cycle Jitter

Multiple frequencies

250

Same frequency

100

tJIT(PER)

Period Jitter

Multiple frequencies

150

tLOCK

Maximum PLL Lock Time

Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT. Parameters are guaranteed by characterization and are not 100% tested.

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