3.

Design Considerations

The following sections provide considerations when implementing the ATTPM20P into a given system.

3.1

SPI Bit Order

The bit order on the SPI Interface is Most Significant bit (MSb) first.

3.2

TPM SPI is Slave Only

The TPM SPI Interface is always configured to be in Slave mode.

3.3

Wait State

The TPM may insert Wait states per the TCG PC Client specification.

3.4

Available Key Storage

The ATTPM20P provides support for the loading of up to ten 2048-bit RSA or ECC keys. These key slots

are in addition to the root keys allocated for the Platform, Storage, and Endorsement Hierarchies (i.e

PPK, SRK, and EK).

3.5

Standard Mode Self-Test

Following a power-up event or a reset, the TPM will execute a series of self-tests of the TPM capabilities.

ATTPM20P splits the TPM power-on self-tests into two groups as defined by the PTP. The initial group is

executed immediately upon TPM power-up. The initial ATTPM20P self-test includes verification of the

RNG and the SHA capabilities for secure boot operations.

The remaining tests of critical internal resources are performed at a later time, either:

•

After the TPM2_SelfTest command is issued, or

•

Upon receipt of the TPM2_IncrementalSelftest command, or

•

Receipt of a command that requires TPM resources that were not tested.

In the event that a TPM command calls an untested resource, the TPM may return TPM_RC_TESTING

and automatically complete internal self-test operations. The requesting software will then be required to

resend the original command.

ATTPM20P

Design Considerations

Datasheet Summary

DS40002082A-page 8