Silicon Errata for the MSC8101 Processor, Mask 0K40A, Rev. 5

Freescale Semiconductor

13

CPM15

Corruption of Port D Registers

Date Added: 5/30/2000

Description: The PDATA, PDATB, PDATC, and PDATD registers can only be written with a

32-bit write instruction. (i.e., stw). When 8- or 16-bit write instructions (i.e., sth, stb) are used, the

bits not being written may be corrupted.

Workaround: Use a 32-bit write instruction only to write to the PDATA, PDATB, PDATC, and

PDATD registers.

System Number: 3679

Fix Plan: Rev A

0K40A

CPM17

Error in Reporting UTOPIA Error Condition

Date Added: 5/30/2000

Description: An FCC receiver which is configured as single PHY master does not detect a UTO-

PIA error condition when SOC and CLAV are not asserted simultaneously.

System Number: 3728

Rev A

0K40A

CPM21

False Indication of Collision in Fast Ethernet

Date Added: 5/30/2000

Description: In the Fast Ethernet a false COL is reported whenever a collision occurs on the pre-

amble of the previous frame.

Workaround: S/W should ignore COL indications when the CRC of the frame is correct.

System Number: 3927

Fix Plan: Rev A

0K40A

CPM22

False Defer Indication in Fast Ethernet

Date Added: 5/30/2000

Description: In the fast ethernet, if a frame is transmitted due to defer and this frame also gets

late collision, a false defer indication is indicated for the next frame.

Workaround: None

System Number: 3981

Fix Plan: Rev A

0K40A

CPM24

Error in Indicating IDLE Between Frame

Date Added: 5/30/2000

Description: In the FCC HDLC transmitter, if slow serial clock (cpm_freq/serial_clock > 16) is

used, RTS does not transition to IDLE between frames. This means that all the frames are trans-

mitted back-to-back in case there is valid data in the transmitter’s FIFO.

Workaround: None

System Number: 3998

Fix Plan: Rev A

0K40A

CPM25

RTS Not Synchronized to Serial Clock

Date Added: 5/30/2000

Description: In the FCC HDLC transmitter in nibble mode, the negation of RTS output signal

is not synchronized to the serial clock. The RTS is negated after the last nibble of the data and

always before the next edge of the serial clock.

Workaround: None

System Number: 4089

Fix Plan: The errata will not be corrected due to minimal system impact and/or availability of

simple work-arounds.

0K40A

Table 2. Silicon Errata (Continued)

Errata

Number

Errata Description

Applies

to Mask