AM29N323D datasheet(19/48 Pages) AMD

19 / 48 page

Am29N323D

August 8, 2002

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations.

The host system may also initiate the chip erase

command sequence while the device is in the unlock

bypass mode. The command sequence is two cycles

cycles in length instead of six cycles. Table 4 shows the

address and data requirements for the chip erase

command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6/DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 13 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 4 shows the address

and data requirements for the sector erase command

sequence.

The device does not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of no less than 50 µs occurs. During the

time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector

erase buffer may be done in any sequence, and the

number of sectors may be from one sector to all sec-

tors. The time between these additional cycles must be

less than 50 µs, otherwise erasure may begin. Any

sector erase address and command following the

exceeded time-out may or may not be accepted. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are accepted.

The interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The

system must rewrite the command sequence and any

additional addresses and commands.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. While the Embedded Erase opera-

tion is in progress, the system can read data from the

non-erasing bank.

The system can determine the status of the erase oper-

ation by reading DQ7 or DQ6/ DQ2 in the erasing bank.

Note that the host system must wait 200 µs after the

last sector erase command to obtain status information

if the first status read is in a different bank than the last

sector selected for erasure. For example, if sector 0,

which is in bank B, was the last sector selected for era-

sure, and the host system requests its first status read

from sector 71, which is in bank A, then the device

requires 200 µs before status information will be avail-

able. Refer to the Write Operation Status section for

information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the sector erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 13 section for timing diagrams.

AM29N323D Datasheet(PDF) 19 Page - Advanced Micro Devices

AM29N323D Datasheet(HTML) 19 Page - Advanced Micro Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datasheet Download

Link URL