AM29N323D datasheet(23/48 Pages) AMD

23 / 48 page

Am29N323D

August 8, 2002

RDY: Ready

The RDY is a dedicated output that indicates (when at

logic low) the system should wait 1 clock cycle before

expecting the next word of data.

RDY functions only while reading data in burst mode.

Three conditions may cause the RDY output to be low:

during the initial access (in burst mode) when PS is

enabled; after the boundary that occurs every 64 words

beginning at address 00000h; and when the clock fre-

quency is less than 6 MHz (in which case RDY is low

every third clock).

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded

Program or Erase algorithm is in progress or complete,

or whether the device has entered the Erase Suspend

mode. Toggle Bit I may be read at any address in the

same bank, and is valid after the rising edge of the final

WE# pulse in the command sequence (prior to the

program or erase operation), and during the sector

erase time-out.

During an Embedded Program or Erase algorithm

operation, successive read cycles to any address

cause DQ6 to toggle. Note that OE# must be low during

toggle bit status reads. When the operation is com-

plete, DQ6 stops toggling.

After an erase command sequence is written, if all

sectors selected for erasing are protected, DQ6

toggles for approximately 100 µs, then returns to

reading array data. If not all selected sectors are pro-

tected, the Embedded Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Note that the host system must wait 200 µs after the

last sector erase command to obtain status information

if the first status read is in a different bank than the last

sector selected for erasure. For example, if sector 0,

which is in bank B, was the last sector selected for era-

sure, and the host system requests its first status read

from sector 71, which is in bank A, then the device

requires 200 µs before status information will be avail-

able.

The system can use DQ6 and DQ2 together to deter-

mine whether a sector is actively erasing or is

erase-suspended. When the device is actively erasing

(that is, the Embedded Erase algorithm is in progress),

DQ6 toggles. When the device enters the Erase

Suspend mode, DQ6 stops toggling. However, the

system must also use DQ2 to determine which sectors

are erasing or erase-suspended. Alternatively, the

system can use DQ7 (see the subsection on DQ7:

Data# Polling).

If a program address falls within a protected sector,

DQ6 toggles for approximately 1

µs after the program

command sequence is written, then returns to reading

array data.

DQ6 also toggles during the erase-suspend-program

mode, and stops toggling once the Embedded

Program algorithm is complete.

See the following for additional information: Figure 4

(toggle bit flowchart), DQ6: Toggle Bit I (description),

Figure 16 (toggle bit timing diagram), and Table 5

(compares DQ2 and DQ6).

Figure 4.

Toggle Bit Algorithm

START

Yes

DQ5 = 1?

Yes

DQ6 = Toggle?

Read Byte

(DQ0-DQ7)

Address = VA

DQ6 = Toggle?

Read Byte Twice

(DQ 0-DQ7)

Adrdess = VA

Read Byte

(DQ0-DQ7)

Address = VA

FAIL

PASS

Note: The system should recheck the toggle bit even if DQ5

= “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

AM29N323D Datasheet(PDF) 23 Page - Advanced Micro Devices

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