Symbol

Alt.

Parameter

Min.

Max.

Unit

Clock frequency

0

1

MHz

Clock pulse width high

260

-

ns

Clock pulse width low

700

-

ns

Input signal rise time

(1)

(1)

ns

Input signal fall time

(1)

(1)

ns

SDA (out) fall time

20 (3)

120

ns

Data in setup time

50

-

ns

Data in hold time

0

-

ns

Data out hold time

50

-

ns

Clock low to next data valid (access time)

-

650

ns

Start condition setup time

250

-

ns

Start condition hold time

250

-

ns

Stop condition setup time

250

-

ns

Time between Stop condition and next Start condition

500

-

ns

Write time

-

5

ms

-

Pulse width ignored (input filter on SCL and SDA)

-

50

ns

1. There is no min. or max. values for the input signal rise and fall times. However, it is recommended by the I²C specification

2. Characterized only, not tested in production.

3. With CL = 10 pF.

4. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA.

that the Rbus × Cbus time constant is within the values specified in Figure 13.

M24128X-FCU

DC and AC parameters

DS12680 - Rev 2

page 22/35