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ES9028PRO Datasheet(PDF) 39 Page - ESS Technology,Inc |
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ES9028PRO Datasheet(HTML) 39 Page - ESS Technology,Inc |
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39 / 57 page  July 6, 2020 CONFIDENTIAL INFORMATION v3.6 ES9028PRO 32-Bit HyperStream® II 8-Channel Audio DAC 39 ESS TECHNOLOGY, INC. 237 South Hillview Drive, Milpitas, CA 95035, USA. Tel (408) 643- 8800 • Fax (408) 643-8801 Register 66-69 (Read-Only): DPLL Number Bits [31:0] Mnemonic dpll_num Default 32’d0 Bit Mnemonic Description [31:0] dpll_num Contains the ratio between the MCLK and the audio clock rate once the DPLL has acquired lock. This value is latched on reading the LSB, so register 66 must be read first to acquire the latest DPLL value. The value is latched on LSB because the DPLL number can be changing as the I2C transactions are performed. FSR = (dpll_num ∗ MCLK) 232 Register 70-93: (Read-Only): SPDIF Channel Status/User Status Bits [191:0] Mnemonic spdif_status Default 192’d0 Bit Mnemonic Description [191:0] spdif_status Contains either the SPDIF channel status (table shown below) or the SPDIF user bits. This selection can be made via register 1 (user_bits). |
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