ADA4355ABCZ datasheet(29/45 Pages) AD

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Data Sheet

ADA4355

Rev. A | Page 29 of 45

CLOCK STABILITY CONSIDERATIONS

Immediately after power-on, the ADA4355 enters an

initialization phase during which an internal state machine sets

up the biases and the registers for proper operation. During the

initialization process, the ADA4355 needs a stable clock. If the

clock source to the ADC is not present or not stable during

ADC power-up, it disrupts the state machine and causes the

ADC to start up in an unknown state. To correct this, invoke a

digital reset via Register 0x08 after the clock source is stable.

Clock instability during normal operation may also necessitate

a digital reset to restore proper operation.

The pseudo code sequence for a digital reset is as follows:

1. Write Register 0x08 = 0x03 for a digital reset.

2. Write Register 0x08 = 0x00 for normal operation.

CONTROLS

The ADA4355 uses four balls to control various functions of

the analog front end. Use the GSEL1 and GSEL0 balls to select

TZ (see Table 9), use the VLDEN ball to enable or disable the

on-chip LDO, and use FSEL to select the filter bandwidth for

the internal LPF. These control balls must be driven as these

balls have no internal pull-up or pull-down resistors.

Transimpedance Gain and Performance Controls

Each TZ determines its relevant saturation current (ISAT) and

input referred rms current noise (IN). The GSEL0 and GSEL1

balls work together as shown in Table 9.

Table 9. Truth Table for GSEL1 and GEL0

GSEL1 (Ball A5)

GSEL0 (Ball A4)

Transimpedance (TZ)

TZ = 2 kΩ

TZ = 20 kΩ

TZ = 200 kΩ

Reserved

LDO Enable Controls

The on-chip 1.8 V LDO is controlled via the VLDEN ball. The

control signal vs. LDO output are shown in Table 10.

Table 10. LDO Control Signal Truth Table

VLDEN (Ball F7)

VLD (Ball F12)

No output

1.8 V

LPF Bandwidth Selection

The ADA4355 uses an internal analog LPF to optimize settling

time and noise performance. The LPF is controlled via the

FSEL ball as shown in Table 11. Input signal pulse width should

be considered when choosing the LPF bandwidth.

Table 11. LPF Truth Table

FSEL (Ball A6)

LPF Bandwidth (MHz)

100

DIGITAL OUTPUT AND TIMING

The ADA4355 supports high speed, digital serial outputs. These

serial differential outputs are LVDS-compatible data and clock

lanes. These output lanes include the D0AP, D0AN, D1AP,

D1AN, DCOP, DCON, FCOP, and FCON balls.

At power-on default, the ADA4355 differential outputs

conform to the ANSI-644 LVDS standard. Each of the LVDS

output driver currents sets a nominal 3.5 mA. A 100 Ω

differential termination resistor placed at the LVDS receiver

inputs results in a nominal 350 mV swing (or 700 mV p-p

differential) at the receiver.

The ADA4355 differential outputs also support a low power,

reduced signal range option (similar to the IEEE 1596.3

standard) via the SPI programming. When operating in

reduced range mode, the LVDS output driver current reduces

to 2 mA. This reduction results in a 200 mV swing (or 400 mV p-p

differential) across a 100 Ω termination at the receiver.

The LVDS outputs facilitate interfacing with LVDS receivers in

custom application specific ICs (ASICs) and FPGAs for

improved switching performance in noisy environments. To

reduce the environmental noise impact, the PCB trace design

recommends single point-to-point net topologies with a 100 Ω

termination resistor placed as close as possible to the receiver.

Timing errors may result if there is no far end receiver

termination, or if there is poor differential trace routing. To

avoid such timing errors, minimize trace lengths and keep the

differential output traces close together and at equal lengths.

Figure 85 shows an example of the FCO and data stream with

proper trace length and position. In Figure 85 and Figure 86,

D0 is the differential signal, D0AP – D0AN, and D1 is the

differential signal, D1AP – D1AN.

D0Ax 500mV/DIV

D1Ax 500mV/DIV

DCOx 500mV/DIV

FCOx 500mV/DIV

4ns/DIV

Figure 85. LVDS Output Timing Example in ANSI-644 Mode (Default)

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