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AT90PWM2 Datasheet(PDF) 39 Page - ATMEL Corporation |
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AT90PWM2 Datasheet(HTML) 39 Page - ATMEL Corporation |
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39 / 365 page ![]() 39 AT90PWM2/3 4317B–AVR–02/05 Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power- save, or Standby) will be activated by the SLEEP instruction. See Table 12 for a sum- mary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The con- tents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. Figure 13 on page 30 presents the different clock systems in the AT90PWM2/3, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Sleep Mode Control Register – SMCR The Sleep Mode Control Register contains control bits for power management. • Bits 3..1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0 These bits select between the five available sleep modes as shown in Table 12. Note: 1. Standby mode is only recommended for use with external crystals or resonators. • Bit 1 – SE: Sleep Enable The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after wak- ing up. Bit 7 6 5 4 3 2 1 0 – – – – SM2 SM1 SM0 SE SMCR Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Table 12. Sleep Mode Select SM2 SM1 SM0 Sleep Mode 000 Idle 0 0 1 ADC Noise Reduction 010 Power-down 011 Reserved 100 Reserved 101 Reserved 1 1 0 Standby (1) 111 Reserved |
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