TJA1124 datasheet(2/23 Pages) NXP

2 / 23 page

NXP Semiconductors

TJA1124

Quad LIN master transceiver

TJA1124

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Product data sheet

Rev. 1 — 8 May 2018

2 / 23

• Very high ESD robustness: ±6 kV according to IEC61000-4-2 for pins LIN1 to LIN4 and

BAT

• Bus terminal and battery pin protected against transients in the automotive environment

(ISO 7637)

• Bus terminal short-circuit proof to battery and ground

• TXD dominant timeout function

• LIN dominant timeout function

• Thermal protection

3 Ordering information

Table 1. Ordering information

Package

Type number

Name

Description

Version

TJA1124AHG[1]

TJA1124BHG[2]

DHVQFN24 plastic dual in-line compatible thermal enhanced very thin quad flat

package; no leads; 24 terminals; body 3.5 × 5.5 × 0.85 mm

SOT 815-1

[1]

The LIN master termination of TJA1124AHG is enabled in Low Power mode.

[2]

The LIN master termination of TJA1124BHG is disabled in Low Power mode

4 Block diagram

VIO

SLP

TXD1

RXD1

TXD2

RXD2

TXD3

RXD3

TXD4

INHN

RXD4

TJA1124

UNDERVOLTAGE

DETECTION

UNDERVOLTAGE

DETECTION

VOLTAGE

REFERENCE

BAT

LIN1

LIN2

LIN3

LIN4

GND

aaa-029893

LIN

TRANSCEIVER

CONTROL

TEMPERATURE

PROTECTION

LIN CHANNEL 4

LIN CHANNEL 3

LIN CHANNEL 2

LIN CHANNEL 1

LIN TRANSCEIVER

VBAT

SYSTEM

CONTROL

Figure 1. Block diagram

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