ZL30791, ZL30795, ZL30793

Product Brief

2

Microsemi Confidential

1. Block Diagram

Figure 1 - Functional Block Diagram

2. Application Example

Figure 2 - Synchronous Ethernet and IEEE 1588 Central Timing Application

PACKET_REF[ 2:0]

Regis ter A c ces s

FracDiv

IntDiv

FracDiv

IntDiv

HP Synthesizer 2

low-jitter

HPOUT6P

HPOUT6N

HPOUT7P

HPOUT7N

DIV

REF0P

DPLL0

Microprocessor Port

SPI or I2C I/F & GPIO Pins

One Diff / Two

Single-Ended

REF0N

REF1P

One Diff / Two

Single-Ended

REF1N

REF2P

One Diff / Two

Single-Ended

REF2N

REF3P

One Diff / Two

Single-Ended

REF3N

REF4P

One Diff / Two

Single-Ended

REF4N

Reference Monitors

& State Machines

DPLL1

DPLL2

HP Synthesizer 1

low-jitter

GP Synthesizer 0

general purpose

GPOUT0

GPOUT1

DIV

DIV

XO

Optional x2

Master

Clock

DIV

HPOUT4P

HPOUT4N

HPOUT5P

HPOUT5N

DIV

DIV

HPOUT0P

HPOUT0N

HPOUT1P

HPOUT1N

DIV

DIV

HPOUT2P

HPOUT2N

HPOUT3P

HPOUT3N

DIV

DIV

GPS (1PPS)

BITS/SSU

Line

Extracted

Clocks[7:0]

TCXO

DPLL0

T4 path

Synth0

1.544 or 2.048MHz

CMOS to BITS/SSU

1 PPS

DPLL1

SyncE

Synth1

2x 156.25MHz

2x 125MHz

155.52MHz, 161.1328125MHz

or other frequency

DPLL2

1588

Control info from

IEEE 1588 algorithm

Synth2

25MHz

1 PPS or clock w/ embedded PPS

1588 signals to

system components

SyncE signals to

system components

to BITS/SSU system

DPLL1 only present on ZL30795 and ZL30793

DPLL2 only present on ZL30793