ZL30791, ZL30795, ZL30793

IEEE 1588 & Synchronous Ethernet

Packet Clock Network Synchronizers

Product Brief

August 2019

1

Microsemi Confidential

Copyright 2019. Microsemi Corporation. All Rights Reserved.

Features

• One, Two or Three DPLL Channels

• Packet and/or physical-layer frequency, phase

and time synchronization

• Physical-layer compliance with ITU-T G.8262,

G.8262.1, G.813, G.812, Telcordia GR-1244,

GR-253

• Packet-timing compliance with ITU-T G.8261,

G.8263, G.8273.2 (class A,B,C&D), G.8273.4

• Enables 5G wireless applications with sub-

100ns time/phase alignment requirements

• Programmable bandwidth, 0.1mHz to 470Hz

• Hitless reference switching and mode switching

• High-resolution holdover averaging

• Programmable phase slope limit for transients,

downto 1 ns/s

• Per-DPLL phase adjustment, 1ps resolution

• Input Clocks

• Accepts up to 10 differential or CMOS inputs

• Any input frequency from 0.5Hz to 900MHz

• Per-input activity and frequency monitoring

• Automatic or manual reference switching

• Fast lock to 1 PPS input, <30 seconds

• Any input can be a 1PPS SYNC input for

REF+SYNC frequency/phase/time locking

• Any input can be a clock with embedded 1PPS

• Per-input phase adjustment, 1ps resolution

• Output Clock Frequency Generation

• Any output frequency from <0.5Hz to 1045MHz

(180MHz max for Synth0)

• High-resolution fractional frequency conversion

with 0ppm error

• Synthesizers 1 & 2 have integer and fractional

dividers to make a total of 5 frequency families

• Output jitter from Synths 1 & 2 is <0.3ps RMS

• Output jitter from fractional dividers is typically

< 1ps RMS, many frequencies <0.5ps RMS

• Each HPOUTP/N pair can be LVDS, LVPECL,

HCSL, 2xCMOS, HSTL or programable diff.

• Four output banks each with VDDO pin; CMOS

output voltages from 1.5V to 3.3V

• Per-synthesizer phase adjust, 1ps resolution

• Per-output programmable duty cycle

• Precise output alignment circuitry and per-

output phase adjustment

• Per-output enable/disable and glitchless

start/stop (stop high or low)

• Local Oscillator

• Operates from a single TCXO or OCXO: 23.75-

25MHz, 47.5-50MHz, 114.285-125MHz

• Very-low-jitter applications can connect a TCXO

or OCXO as the stability reference and a low-

jitter XO as the jitter reference

• General Features

• Automatic self-configuration at power-up from

internal Flash memory

• Input-to-output alignment <2ns

• Internal compensation (1ppt) for local oscillator

frequency error in DPLLs and input monitors

• Numerically controlled oscillator behavior in

each DPLL and each fractional output divider

• Programmable Time of Day counters

• Easy-to-configure design requires no external

VCXO or loop filter components

• 7 GPIO pins with many possible behaviors

• 1.8V and 3.3V core VDD voltages

• Power: 1.3W for 2 inputs, 1 synth, 6 LVDS out

• Easy-to-use evaluation/programming software

• Factory programmable power-up configuration

Applications

•

Central system timing ICs for SyncE and/or

IEEE 1588, SONET/SDH, OTN, wireless base

station and other carrier-grade systems

•

G.8262/813 EEC/SEC, Telcordia Stratum 2-4

Ordering Information

ZL30791LFG7

1-Channel

80-lead LGA Trays

ZL30795LFG7

2-Channel

80-lead LGA Trays

ZL30793LFG7

3-Channel

80-lead LGA Trays

NiAu (Pb-free)

Package size: 11 x 11 mm

-40C to +85C