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L6986ITR Datasheet(PDF) 25 Page - STMicroelectronics |
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L6986ITR Datasheet(HTML) 25 Page - STMicroelectronics |
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25 / 60 page ![]() whereas the zero is defined as: fPHF= 1 2∙π∙R0∙C0+Cp (15) 5.3 Voltage divider The contribution of the internal voltage divider for fixed output voltage devices is: GDIV(s)= R2R1+R2=VFBVOUT (16) A small signal capacitor in parallel to the upper resistor (see figure below) of the voltage divider implements a leading network (fzero < fpole), sometimes necessary to improve the system phase margin: Figure 28. Leading network example The Laplace transformer of the leading network is: GDIV(s)= R2R1+R2∙1+sfZ1+sfP (17) where fZ= 12∙π∙R1∙CR1 (18) fP= 1 2∙π∙R1∙R2 R1+R2∙CR1 fZ<fP 5.4 Total loop gain In summary, the open loop gain can be expressed as: G (s)= GDIV(s)∙GC0(s)∙A0(s) (19) L6986I Voltage divider DS13647 - Rev 1 page 25/60 |
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