MCP47FVB01 datasheet(33/92 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS20005429B-page 33

MCP48FEBXX

4.2.6

WIPERLOCK TECHNOLOGY

The MCP48FEBXX device’s WiperLock technology

allows application-specific device settings (DAC

requiring the use of an additional write-protect pin.

There are two configuration bits (DLx:CLx) for each

DAC (DAC0 and DAC1).

Dependent on the state of the DLx:CLx configuration

bits, WiperLock technology prevents the serial

commands from the following actions on the DACx

registers and bits:

• Writing to the specified volatile DACx Register

memory location

• Writing to the specified nonvolatile DACx Register

memory location

• Writing to the specified volatile DACx

configuration bits

• Writing to the specified nonvolatile DACx

configuration bits

Each pair of these configuration bits control one of four

modes. These modes are shown in Table 4-3. The

addresses for the configuration bits are shown in

Table 4-1.

To modify the configuration bits, the HVC pin must be

forced to the VIHH state and then receive an enable or

disable command on the desired pair of DAC Register

addresses.

Please refer to Section 7.4 “Enable Configuration

Bit”

and Section 7.5 “Disable Configuration Bit”

commands for operation.

4.2.6.1

POR/BOR Operation with

WiperLock Technology Enabled

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

Volatile DAC0 (DAC1) register values with the

Nonvolatile DAC0 (DAC1) register values.

Note:

To modify the CL0 bit, the enable or

disable command specifies address 00h,

while to modify the DL0 bit, the enable or

disable command specifies address 10h.

Note:

During device communication, if the

Device Address/Command combination is

invalid or an unimplemented Address is

specified, then the MCP48FEBXX will

Command Error that Command byte. To

reset the serial interface state machine,

the CS pin must be driven to the inactive

state (VIH) before returning to the active

state (VIL or VIHH).

TABLE 4-3:

WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS - FUNCTIONAL DESCRIPTION

Comments

DACx

DACx Configuration (2)

Volatile

Nonvolatile

Volatile

Nonvolatile

Locked

All DACx registers are locked.

Locked

Unlocked

Locked

All DACx registers are locked except volatile DACx

Configuration registers.

This allows operation of power-down modes.

Unlocked

Locked

Unlocked

Locked

Volatile DACx registers unlocked, nonvolatile DACx

registers locked.

Unlocked

All DACx registers are unlocked.

Note 1:

The state of these configuration bits (DLx:CLx) are reflected in WLxB:WLxA bits as shown in Register 4-6.

DAC configuration bits include Voltage Reference Control bits (VRxB:VRxA), Power-Down Control bits

(PDxB:PDxA), and Output Gain bits (Gx).

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