MCP47FVB01 datasheet(58/92 Pages) MICROCHIP

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MCP48FEBXX

DS20005429B-page 58

 2015 Microchip Technology Inc.

7.1

Write Command

Write commands are used to transfer data to the

desired memory location (from the Host controller). The

Write

command can be issued to both the volatile and

nonvolatile memory locations.

Write commands can be structured as either Single or

Continuous.

The format of the command is shown in Figures 7-3

(Single) and 7-4 (Continuous).

A write command to a volatile memory location

changes that location after a properly formatted write

command has been received.

A write command to a nonvolatile memory location will

start an EEPROM write cycle only after a properly

formatted write command has been received and the

CS pin transitions to the inactive state (VIH).

7.1.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

active state (VIL). Typically, the CS pin will be in the

inactive state (VIH) and is driven to the active state

(VIL). The 24-bit Write command (Command Byte

and Data Bytes) is then clocked in on the SCK and

SDI pins. Once all 24 bits have been received, the

specified volatile address is updated. A write will not

occur if the Write command isn’t exactly 24 clock

pulses. This protects against system issues corrupting

the nonvolatile memory locations.

Figures 7-5 and 7-6 show the waveforms for a single

write (depending on SPI mode).

7.1.2

SINGLE WRITE TO NONVOLATILE

MEMORY

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile

memory with the exception that after the CS pin is

driven inactive (VIH), the EEPROM write cycle (tWC) is

started. A write cycle will not start if the Write

command isn’t exactly 24 clock pulses. This protects

against system issues corrupting the nonvolatile

memory locations.

Once a write command to a nonvolatile memory

location has been received, no other SPI commands

should be received before the CS pin transitions to the

inactive state (VIH), or the current SPI command will

have a Command Error (CMDERR) occur.

After the CS pin is driven inactive (VIH), the serial

interface may immediately be re-enabled by driving

the CS pin to the active state (VIL).

During an EEPROM write cycle, access to the volatile

memory is allowed when using the appropriate

command

sequence.

Commands

that

address

nonvolatile memory are ignored until the EEPROM

write cycle (tWC) completes. This allows the Host

Controller to operate on the volatile DAC registers.

Figures 7-5 and 7-6 show the waveforms for a single

write (depending on the SPI mode).

Note 1:

Writes to certain memory locations will be

dependent

the

state

the

WiperLock™ technology status bits.

During device communication, if the

Device Address/Command combination is

invalid or an unimplemented Device

Address

specified,

then

the

MCP48FEBXX will generate a Command

Error state. To reset the SPI state

machine, the CS pin must transition to the

inactive state (VIH).

Note:

The EEWA status bit indicates if an

EEPROM write cycle is active (see

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