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LP3971 Datasheet(PDF) 33 Page - National Semiconductor (TI) |
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LP3971 Datasheet(HTML) 33 Page - National Semiconductor (TI) |
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33 / 42 page  I 2C Register Definitions (Continued) I 2C DVM TIMING FOR VCC APPS (Buck 1) 20180718 LP3971 Controls DIGITAL INTERFACE CONTROL SIGNALS Signal Definition Active State Signal Direction SYS_EN High Voltage Power Enable High Input PWR_EN Low Voltage Power Enable High Input SCL Serial Bus Clock Line Clock Input SDA Serial Bus Data Line Bidirectional nRSTI Forces an Unconditional Hardware Reset Low Input nRSTO Forces an Unconditional Hardware Reset Low Output nBATT_FLT Main Battery Removed or Discharged Indicator Low Output PWR_ON Wakeup Input to CPU High Input nTEST_JIG Wakeup Input to CPU Low Input SPARE Wakeup Input to CPU High/Low* Input EXT_WAKEUP Wake-Up Output for Application Processor High Output GPIO1/nCHG_EN General Purpose I/O/External Back-Up Battery Charger -/Low Bidirectional/Input GPIO2 General Purpose I/O - Bidirectional * POWER DOMAIN ENABLES PMU Output HW Enable SW Enable LDO_RTC - - LDO1 SYS_EN LDO1_EN LDO2 SYS_EN LDO2_EN LDO3 SYS_EN LDO3_EN LDO4 PWR_EN/SYS_EN LDO4_EN LDO5 PWR_EN/SYS_EN LDO5_EN BUCK1 PWR_EN B1_EN BUCK2 SYS_EN/PWR_EN B2_EN BUCK3 SYS_EN B3_EN LDO_RTC TRACKING (nIO_TRACK) LP3971 has a tracking function (nIO_TRACK). When en- abled, LDO_RTC voltage will track LDO1 voltage within 200 mV down to 2.8V when LDO1 is enabled. This function can be switched on/off by BPTR (8h’0E) register bit. LDO4, LDO5 AND BUCK 2 ENABLE SELECTION (LDO4_ESEL, LDO5_ESEL AND BUCK2_ESEL) LDO4, 5 and BUCK2 power domain enable is possible to change between SYS_EN and PWR_EN by register bits. WAKE-UP FUNCTIONALITY (PWR_ON, nTEST_JIG, SPARE AND EXT_WAKEUP) Three input pins can be used to assert wakeup output for 10 ms for application processor notification to wakeup. SPARE input can be programmed through I 2C compatible interface www.national.com 33 |
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