9.

Read Operations

Read operations are initiated the same way as write operations with the exception that the Read/Write Select bit in

the device address byte must be a logic ‘1’. There are multiple read operations supported by the device:

• Current Address Read

• Random Address Read

• Sequential Read

Note: 

The AT24CSW01x/AT24CSW02x contains a single Address Pointer register, which is shared by both the EEPROM

and the Security register. As such, when changing from one region to the other, the first read operation in the

new region should begin with a dummy write sequence (i.e. a random read operation with the new region’s device

address and word address bytes) in order to ensure the Address Pointer is set to a known value. See Read

Operations in the Security Register for additional requirements on read operations in the Security register.

9.1

Current Address Read

The internal data word address counter maintains the last address accessed during the last read or write operation,

address roll-over during a read is from the last byte of the last page to the first byte of the first page of the memory.

A current address read operation will output data according to the location of the internal data word address counter.

This is initiated with a Start condition, followed by a valid device address byte with the R/W bit set to logic ‘1’. The

device will ACK this sequence and the current address data word is serially clocked out on the SDA line. All types

of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start

condition to begin the next sequence.

Figure 9-1. Current Address Read

SCL

SDA

Device Address Byte

Data Word (n)

Start

by

Host

ACK

from

Client

NACK

from

Host

Stop

by

Host

MSb

MSb

1

0

1

0

#

#

#

1

0 D7 D6 D5 D4 D3 D2 D1 D0 1

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

Note:  # indicates the hardware address value which is managed by the ordering code of the device (see Table 6-2).

9.2

Random Read

A random read begins in the same way as a byte write operation does to load in a new data word address. This is

known as a “dummy write” sequence; however, the data byte and the Stop condition of the byte write must be omitted

to prevent the part from entering an internal write cycle. Once the device address and word address are clocked in

and acknowledged by the EEPROM, the bus host must generate another Start condition. The bus host now initiates

a current address read by sending a Start condition, followed by a valid device address byte with the R/W bit set to

logic ‘1’. The EEPROM will ACK the device address and serially clock out the data word on the SDA line. All types

of read operations will be terminated if the bus host does not respond with an ACK (it NACKs) during the ninth clock

cycle. After the NACK response, the host may send a Stop condition to complete the protocol, or it can send a Start

condition to begin the next sequence.

AT24CSW01X/AT24CSW02X

Read Operations

and its subsidiaries

Datasheet

DS20006396B-page 25