Note:  While the lower order 16 bytes of the Security register are read-only, the device will ACK if the Read/Write

Select bit is a logic ‘0’.

Table 6-1. Device Address Byte

Memory Region

Device Type Identifier

Hardware Client Address Bits

R/W

Select

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEPROM Array

1

0

1

0

A2

A1

A0

R/W

Security Register and

Write Protection Register

1

0

1

1

A2

A1

A0

R/W

Table 6-2. Hardware Address Response by Part Number

Part Number Series

Hardware Address Bits

1-Kbit

2-Kbit

A2

A1

A0

AT24CSW010

AT24CSW020

0

0

0

0

0

1

0

1

0

0

1

1

1

0

0

1

0

1

1

1

0

1

1

1

Note: 

1.

Contact your local sales representative for hardware client address availability.

For all operations other than a current address read, a word address byte must be transmitted to the device

immediately following the device address byte. The word address byte contains a 7-bit (in the case of the

AT24CSW01x) or 8-bit (in the case of the AT24CSW02x) memory array word address, and is used to specify which

byte location in the EEPROM to start reading or writing. Refer to Table 6-3 to review these bit positions.

When accessing the Security register, it is required that the A7 and A6 bits of the word address be set to ‘10’

respectively. These bits are at a higher order address range than what is needed to address the 32 byte space

(A4 through A0). It is recommended that all address bits that fall outside the address range that do not have other

requirements be set to a logic ‘0’.

Table 6-3. Word Address Byte

Memory Region

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

EEPROM Array

A7(1)

A6

A5

A4

A3

A2

A1

A0

Security Register

1

0

X

A4

A3

A2

A1

A0

Security Register Lock Function

0

1

1

0

X

X

X

X

Write Protection Register

1

1

X

X

X

X

X

X

Note: 

1.

Bit 7 is a “don't care” bit on the AT24CSW01x.

AT24CSW01X/AT24CSW02X

Memory Organization

and its subsidiaries

Datasheet

DS20006396B-page 17