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AT25SL321 Datasheet(PDF) 33 Page - Dialog Semiconductor |
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AT25SL321 Datasheet(HTML) 33 Page - Dialog Semiconductor |
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33 / 82 page ![]() 32 AT25SL321 DS-25SL321–112H–2020-10 8.15 Page Program (02h) This instruction programs the memory to 0. A Write Enable instruction must be issued before the device accepts this instruction (Status Register bit WEL = 1). After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL). The instruction is entered by driving the CS pin low, then sending the instruction code 02h with a 24-bits address (A23-A0) and at least one data byte, into the SI pin. The CS pin must be driven low for the entire time of the instruction while data is being sent to the device. (See Figure 8-22 and Figure 8-23). If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) is set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing must wrap to the beginning of the page. In some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes within the same page. One condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. If more than 256 bytes are sent to the device, the addressing must wrap to the beginning of the page and overwrite previously sent data. The CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done, this instruction cannot be executed. After CS is driven high, the self-timed Page Program instruction commences for a time duration of tPP (see Section 9.8, AC Electrical Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction can still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions. When the BUSY bit is asserted, the Write Enable Latch (WEL) bit in the Status Register is cleared to 0. Figure 8-22. Page Program Instruction (SPI Mode) |
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