DS31256_V01 datasheet(169/183 Pages) MAXIM

169 / 183 page

DS31256 256-Channel, High-Throughput HDLC Controller

169 of 183

AC CHARACTERISTICS: LAYER 1 PORTS

(VDD = 3.0V to 3.6V, TA = 0°C to +70°C.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

(Note 9)

100

RC/TC Clock Period

(Note 10)

(Note 9)

RC/TC Clock Low Time

(Note 10)

(Note 9)

RC/TC Clock High Time

(Note 10)

(Note 9)

RD Setup Time to the Falling Edge or

Rising Edge of RC

(Note 10)

RS/TS Setup Time from the Falling

Edge or Rising Edge of RC/TC

(Note 9)

t1 - 10

(Note 9)

RD Hold Time from the Falling Edge or

Rising Edge of RC

(Note 10)

RS/TS Hold Time from the Falling Edge

or Rising Edge of RC/TC

(Note 9)

t1 - 10

(Note 9)

Delay from the Rising Edge or Falling

Edge of TC to Data Valid on TD

(Note 10)

Note 9: Ports 0 to 15 in applications running up to 10MHz.

Note 10: Port 0, 1, or 2 running in applications up to 52MHz.

Note 11: Aggregate, maximum bandwidth and port speed for the DS31256 are directly proportional to PCLK frequency. Throughput

measurements are made at PCLK = 33MHz.

Figure 13-1. Layer 1 Port AC Timing Diagram

RC[n] / TC[n]

Normal Mode

RD[n] / RS[n] /

TS[n]

TD[n]

RC[n] / TC[n]

Inverted Mode

l1 ac

Note: TC and RC are independent of each other. In the above timing diagram, all the signals beginning with “T” reference the

transmit clock TC; all signals beginning with “R” reference the receive clock RC.

DS31256 Datasheet(PDF) 169 Page - Maxim Integrated Products

DS31256 Datasheet(HTML) 169 Page - Maxim Integrated Products

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL