ADP5076 datasheet(22/23 Pages) AD

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ADP5076

Data Sheet

Rev. A | Page 22 of 23

LAYOUT CONSIDERATIONS

Layout is important for all switching regulators but is particularly

important for regulators with high switching frequencies. To

achieve high efficiency, good regulation, good stability, and low

noise, a well-designed PCB layout is required. Follow these

guidelines when designing PCBs:



Keep the input bypass capacitor (CIN) near to the PVIN pin

and the AVIN pin.



Keep the high current paths as short as possible. These

paths include the connections between CIN, L1, D1, COUT1

and the PGND pin for the boost regulator, and L2, D2,

COUT2, and the PGND pin for the inverting regulator and

their connections to the ADP5076.



Keep the AGND pin and the PGND pin separate on the

top layer of the board. This separation avoids pollution of

the AGND pin with switching noise. Connect both the

AGND and PGND pins to the board ground plane with

vias. Ideally, connect the PGND pin to the plane at a point

between the input and output capacitors.



Keep high current traces as short and wide as possible to

minimize parasitic series inductance, which causes spiking

and EMI.



Avoid routing high impedance traces near any node

connected to the SW1 and SW2 pins or near inductors L1

and L2 to prevent radiated switching noise injection.



Place the feedback resistors (RFT1, RFB1, RFT2, and RFB2) as close

as possible to the FB1 and FB2 pins to prevent high frequency

switching noise injection.



Place the tops of the upper feedback resistors (RFT1 and RFT2) or

route traces to them from as close as possible to the tops of

COUT1 and COUT2 for optimum output voltage sensing.



Place the compensation components (RC1, CC1, RC2, and

CC2) as close as possible to the COMP1 and COMP2 pins.

Do not share vias to the ground plane with the feedback

resistors to avoid coupling high frequency noise into the

sensitive COMP1 and COMP2 pins.



Place the CVREF capacitor as close to the VREF pin as

possible. Ensure that short traces are used between the

VREF pin and RFB2.

COUT1

COUT2

VNEG

VPOS

RFT1

RFT2

RFB1

RFB2

RC1

RC2

CC2

CIN

CC1

CVREF

Figure 48. Suggested Layout for VIN = +3.3 V, VPOS = +15 V, ILOAD1 = 90 mA and

VNEG = −15 V, ILOAD2 = 60 mA, Not to Scale

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