VSC8021 datasheet(6/17 Pages) VITESSE

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8021/VSC8022

2.5Gb/s SONET-Compatible

8-Bit MUX/DEMUX Chipset

Page 6

G52028-0, Rev 4.1

05/25/01

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

Table 2: VSC8022 Demultiplexer AC Characteristics

NOTE: (1) If t C changes, all the remaining parameters change as indicated by the equations.

DC Characteristics

Table 3: Low Speed ECL Inputs and Outputs

(Over recommended operating range with internal VREF, VCC = GND, output load = 50Ω to -2.0V)

Note: Differential ECL output pins must be terminated identically.

Table 4: High-Speed Inputs and Outputs

(Over recommended operating conditions, VCC = GND, Output load = 50Ω to -2.0V)

NOTES: (1) A reference generator is built in to each high-speed input, and these inputs are designed to be AC-coupled.

(2) If a high-speed input is used single-ended, a 150pF capacitor must be connected between the unused high-speed or comple-

ment input and the power supply (VTT).

(3) Differential high-speed outputs must be terminated identically.

Parameter

Description

Min

Typ

Max

Units

Conditions

Clock period(1)

400

BYTE clock period (tD = tC x 8) (framed)

3.2

tBD

BYTE clock output to valid data

0.5

1.0

2.0

tDFP

FP rising edge from parallel data output

change from A1 to A2 (tDFP = tD)

3.2

tPFP

FP pulse width (tPFP = tD)3.2

tOOFN

OOFN falling edge before A1 chan

ges to A2 (tOOFN = tD x 4)

12.8

tOOFNPW

OOFN pulse width (tOOFNPW = tD)3.2

Phase

Margin

Serial data phase timing margin with respect

to high-speed clock:

135

180

degrees

Parameter

Description

Min

Typ

Max

Units

Conditions

VOH

Output HIGH voltage

-1020

-700

VIN = VIH (max) or VIL (min)

VOL

Output LOW voltage

VTT

-1620

VIN = VIH (max) or VIL (min)

VIH

Input HIGH voltage

-1150

-600

Guaranteed HIGH signal for

all inputs

VIL

Input LOW voltage

VTT

-1500

Guaranteed LOW signal for

all inputs

∆V

OUT

Output voltage swing

0.8

1.0

1.4

Output load 50

Ω to V

Parameter

Description

Min

Typ

Max

Units

Conditions

∆V

Input voltage swing

0.8

1.0

1.2

AC-coupled

VOH

Output HIGH voltage

-0.9

Output load, 50

Ω to -2.0V

VOL

Output LOW voltage

-1.8

Output load, 50

Ω to -2.0V

∆V

OUT(DATA)

Output voltage swing for data

0.6

0.8

1.2

Output load, 50

Ω to -2.0V

∆V

OUT(clk)

Output voltage swing for clock

0.6

0.7

1.2

Output load, 50

Ω to -2.0V

-------------------

–





360

Phase Margin =

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